Skip to content
View lefmylonas's full-sized avatar
  • ECE Department, University of Patras

Highlights

  • Pro

Block or report lefmylonas

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don't include any personal information such as legal names or email addresses. Markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
7 results for source starred repositories written in SystemVerilog
Clear filter

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

SystemVerilog 1,657 659 Updated Sep 19, 2025

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

SystemVerilog 1,136 480 Updated May 26, 2025

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

SystemVerilog 446 187 Updated May 15, 2025

Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software …

SystemVerilog 112 29 Updated Sep 18, 2023

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

SystemVerilog 96 17 Updated Oct 31, 2025

Demo: how to create a custom EBRICK

SystemVerilog 23 2 Updated Nov 20, 2024

PULPissimo, PULP-SDK and PULP-RUNTIME exercises

SystemVerilog 6 11 Updated Dec 18, 2020