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  • ECE Department, University of Patras

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7 results for source starred repositories written in Verilog
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Verilog 1,735 385 Updated Nov 5, 2025

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.githu…

Verilog 527 148 Updated Mar 26, 2025

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

Verilog 58 11 Updated May 29, 2025

Zynq-7000 DPU TRD

Verilog 46 18 Updated Jul 19, 2019

Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization

Verilog 34 3 Updated May 29, 2025

Example designs for using Ethernet FMC without a processor (ie. state machine based)

Verilog 32 8 Updated Nov 21, 2024

RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and generative AI with configurable precision (FP32/16/BF16/INT8).

Verilog 17 2 Updated Apr 25, 2025