Researcher at Applied Electronics Laboratory (APEL lab)
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ECE Department, University of Patras
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Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM). . . . . . Online tutorial: https://google.githu…
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
Example designs for using Ethernet FMC without a processor (ie. state machine based)
RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and generative AI with configurable precision (FP32/16/BF16/INT8).