Send video/audio over HDMI on an FPGA

A directory of Western Digital’s RISC-V SweRV Cores

This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no cluster.

4 stage, in-order, compute RISC-V core based on the CV32E40P