PicoRV32 - A Size-Optimized RISC-V CPU

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

SERV - The SErial RISC-V CPU

mor1kx - an OpenRISC 1000 processor IP core

Open source retro ISA video card

🎹 Low-level emulator for SA-synthesis pianos plugin

CPU microarchitecture, step by step

FPGA implementation of DEC PDP-1 computer (1959) in Verilog, with CRT, Teletype and Console.

FPGA based MIT CADR lisp machine - rewritten in modern verilog - boots and runs

Pano Logic G2 Reverse Engineering Project

A Full Hardware Real-Time Ray-Tracer

PanoLogic Zero Client G1 reverse engineering info

A self-hosting Forth for J1-style CPUs