PCIE 5.0 Graduation project (Verification Team)

AMBA AHB 5.0 VIP in SystemVerilog based on UVM

UVM VIP for Single Port RAM Synchronous Read/Write

UVM Test bench for a 8-bit ALU

UVM and Systemverilog based test benches for functional verification of a RAM module

Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.

An UVM example of UART

an infrastructure to implement arbitrary indirect registers on top of uvm

为了学习UVM验证相关知识，需要动手尝试实际的项目。作为一个初学者，难以接触到实际的项目，于是我从夏宇闻老师的《Verilog数字系统设计教程》一书中，挑选出一个简单的小设计，作为我的验证对象，并围绕它编写了UVM验证环境。

UVM verification component and testbench generator tool

Implements a simple UVM based testbench for a simple memory DUT.

Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Both SPI and I2C are robust, stable communication protocols tha…

SystemVerilog UVM testbench example

General Purpose I/O agent written in UVM

This script builds the UVM register model, based on pre-defined address map in markdown (mk) style

Verification IP for AMBA APB Protocol

VIP for AXI Protocol

UVM Testbench to verify serial transmission of data between SPI master and slave

This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

my UVM training projects

DOULOS Easier UVM Code Generator

Novel GUI Based UVM Testbench Template Builder

AMBA AHB 2.0 VIP in SystemVerilog UVM

System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment

UVM Generator

uvm auto generator

UVM interactive debug library

uvm AXI BFM(bus functional model)

This is the main repository for all the examples for the book Practical UVM

A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology