opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Must-have verilog systemverilog modules

RISC-V CPU Core (RV32IM)

OpenXuantie - OpenC910 Core

MIPS CPU implemented in Verilog

Verilog implementation of a RISC-V core

奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）

Naïve MIPS32 SoC implementation