cocotb: Python-based chip (RTL) verification

VHDL/Verilog/SystemC code generator, simulator API written in python/c++

Control and status register code generator toolchain

🐌Yet Another Simulation Architecture

Generate UVM register model from compiled SystemRDL input

EasierUVM from Doulos now written in Python for easier UVM with framework and template generator

Generic testbench for RISC-V CPUs

Generate the uvm testbench automatically

GUI based UVM Test Environment generation tool

Python-based IP-XACT parser

Automatic testbench and reference flow generation tool compatible with UVM and SVA.

UVM Command Center - UVM Testbench Builder (DEMO) - Demo of UVM Verification Workflow IDE.

TB_LINT - Modular Linting Framework

Transparent suspend/resume runtime enabling preemptible GPU workloads via memory snapshotting, UVM paging, and execution state orchestration.

VeriScribe is a documentation generator tool for SystemVerilog projects.