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uvm
Here are 18 public repositories matching this topic...
Control and status register code generator toolchain
asic fpga eda verilog csr command-line-tool systemverilog uvm registers axi amba apb register-descriptions systemrdl-compiler hardware-description-language uvm-register-model
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Dec 3, 2025 - Python
Generate UVM register model from compiled SystemRDL input
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Nov 25, 2025 - Python
GUI based UVM Test Environment generation tool
python testing script perl rtl verilog systemverilog automated uvm testbench uvm-component uvmg-alpha
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Nov 22, 2020 - Python
Automatic testbench and reference flow generation tool compatible with UVM and SVA.
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Nov 13, 2020 - Python
Generate the uvm testbench automatically
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Mar 27, 2024 - Python
UVM Command Center - UVM Testbench Builder (DEMO) - Demo of UVM Verification Workflow IDE.
workflow asic fpga templates ide verification eda uvm testbench uvm-command-center uvm-testbench-builder uvm-workflow-ide
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Apr 14, 2024 - Python
TB_LINT - Modular Linting Framework
lint asic linter rtl verilog systemverilog uvm naturaldocs verilator systemverilog-hdl systemverilog-simulation systemverilog-parser verible systemverilog-test-bench systemverilog-language
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Nov 24, 2025 - Python
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