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uvm

Here are 4 public repositories matching this topic...

rggen / rggen-sample-testbench

vhdl verilog systemverilog uvm uvm-ral-model uvm-register-model

Updated Dec 19, 2025
VHDL

angeliaplutus / ipcoredesign

Design & Verification of IP Cores and ICs, Artificial Intelligence

verification artificial-intelligence hardware-designs uvm osvvm uvvm cocotb design-of-ip-cores-and-ics

Updated Jul 9, 2024
VHDL

npatsiatzis / uart

vhdl systemverilog uvm verilator cocotb pyuvm

Updated Oct 7, 2023
VHDL

cong2738 / May_team_project_I2C_SPI

UVM based Verification of SPI_Protocol and I2C_Protoccol. A Serial intra System Communication Peripheral Protocol

c fpga i2c verilog spi vivado systemverilog uvm verdi microblaze axi hardware-description-language basys3-fpga synopsys-vcs

Updated Jul 24, 2025
VHDL

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