xrt

Here are 17 public repositories matching this topic...

adilsondias-engineer / vd100-ps-ma-client

PS userspace XRT application for the VD100 MA Crossover AIE-ML v2 pipeline. Drives mm2s/s2mm HLS kernels and mygraph via XRT 2025.2 on XCVE2302. Includes golden test vector validation and XRT lifecycle performance analysis.

c-plus-plus fpga cpp amd yocto embedded-linux versal moving-average xrt cortex-a72 xilinix vd100 aie-ml xvce2032 hls-kernel

Updated Apr 13, 2026
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adilsondias-engineer / vd100-aie-pipeline

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First documented end-to-end PL + AIE-ML + PS pipeline on Versal AI Edge XCVE2302 (VD100). MA crossover trading signal via HLS DMA + AIE graph + XRT host app. No VCK190. No MATLAB. Ethereum audit log on Hardhat.

fpga hls amd xilinx yocto embedded-linux versal trading-systems moving-average xrt vitis xcve2302 aie-ml

Updated Apr 11, 2026
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aditya2819 / Optimizing-Serpens-SpMV-Accelerator-on-Xilinx-Alveo-U280

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High-throughput Sparse Matrix–Vector Multiply (SPMV) accelerator for the Xilinx Alveo U280, redesigned from Serpens A16 into a fully Vitis HLS dataflow kernel with 24 HBM channels and improved memory and parallelism.

fpga cpp linear-algebra high-performance-computing xilinx xilinx-fpga high-level-synthesis xrt fpga-programming xilinx-vitis high-bandwidth-memory xilinx-alveo-u280

Updated Dec 3, 2025
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adilsondias-engineer / vd100_ma_system_project

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Vitis 2025.2 system project for VD100 (XCVE2302) — v++ link + package for AIE-ML v2 + HLS kernel integration. Produces aie.xclbin and BOOT.BIN CDO artifacts. Reusable: swap AIE kernel or add HLS kernels without new project.

fpga hls amd xilinx versal xrt bootgen vitis xcve2302 vd100 aie-ml xclbin mm2s s2mm

Updated Apr 11, 2026
CMake

boada / swiftXRT

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version tracking for the swift analysis in support of the planck clusters

swift astronomy xrt

Updated Jan 6, 2021
Jupyter Notebook

adilsondias-engineer / versal-ai-edge-vd100-linux

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Custom Yocto Linux bring-up on Alinx VD100 (XCVE2302). v1: SD/Ethernet/USB. v2: I2C/GPIO/PL LED/kernel driver. v3: XRT + AIE-ML pipeline + Ethereum. No VCK190. No MATLAB. AMD EDF 25.11 / Scarthgap.

fpga ethereum device-tree ethereum-contract vivado yocto embedded-linux uboot versal xrt libgpiod cortex-a72 amd-xilinx xcve2302 vd100 system-device-tree aie-ml zocl

Updated Apr 13, 2026

steleman / xrt-202420.2.18.179-fc39

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Clone of AMD / Xilinx XRT repo from https://github.com/Xilinx/XRT. Major patches and builds / works on Fedora 39.

fpga fedora linux-kernel xilinx xrt vitis

Updated Apr 12, 2025
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adilsondias-engineer / vd100-aie-ma-crossover

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AIE-ML v2 moving average crossover kernel for VD100 (XCVE2302). Dual MA (fast 10 / slow 50 period), BUY/SELL/HOLD signal. 56 int32 samples/iteration via HLS DMA. Used in vd100-aie-pipeline. Vitis 2025.2.

fpga hls amd signal-processing xilinx versal trading-systems moving-average xrt vitis xcve2302 vd100 aie-ml

Updated Apr 11, 2026
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GeertRoks / AMD-Versal-phylogenetic-likelihood-function

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Implementation of the Phylogenetic Liklihood Function for the AMD Versal architecture (FPGA and AI processors on same SoC).

fpga cpp amd phylogenetics versal phylogenetic-analysis xrt plf

Updated Nov 27, 2024
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adilsondias-engineer / vd100-ma-trading-signal

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Live Binance WebSocket feed → MA crossover signal → Ethereum smart contract on Versal AI Edge XCVE2302 (VD100). SW mode: 1440ns on A72. AIE-ML v2 XRT pipeline integrated and benchmarked. XRT architectural findings documented.