amd-xilinx

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Here are 6 public repositories matching this topic...

j-schacht / xilinx_zcu102_trustzone_demo

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Tutorial and base project: TEE on AMD Zynq UltraScale+ using Arm TrustZone

xilinx yocto fpga-soc-linux aarch64 fpga-soc petalinux trustzone tee xilinx-zynq op-tee arm-trustzone amd-xilinx

Updated Apr 10, 2024
C

Un2versidad / Digital-Logic

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Introduction to VHDL and Digital Logic - Basys 3 and Vivado Projects Repository

website documentation fpga hardware amd vhdl eda rtl verilog xilinx educational uip vivado xilinx-fpga educational-materials xilinx-vivado constrains xdc amd-xilinx

Updated Apr 25, 2025
Tcl

solomontesema / qcrate

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Distributed FPGA instrumentation platform using SystemVerilog, AXI/APB, DMA, PetaLinux, FreeRTOS/OpenAMP, and deterministic timing.

fpga freertos xilinx systemverilog fpga-soc petalinux dma embedded-linux axi rpmsg openamp zynqmp amd-xilinx kria-kv260

Updated Sep 14, 2026
Python

Aneein / RK-XCKU5P-F-Board-Part

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Vivado board part for the RIGUKE RK-XCKU5P-F V1.2 (XCKU5P-FFVB676-2-I): board definition, pin map, IP presets, and the XDMA GTY_Quad_224 placement fix for PCIe Gen3 x4.

fpga tcl xilinx vivado board-files pcie fmc ddr4 xdma mipi-csi ultrascale-plus amd-xilinx xcku5p qsfp28 kintex-ultrascale-plus board-part

Updated Sep 23, 2026
Tcl

adilsondias-engineer / versal-ai-edge-vd100-linux

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Custom Yocto Linux bring-up on Alinx VD100 (XCVE2302). v1: SD/Ethernet/USB. v2: I2C/GPIO/PL LED/kernel driver. v3: XRT + AIE-ML pipeline + Ethereum. No VCK190. No MATLAB. AMD EDF 25.11 / Scarthgap.

fpga ethereum device-tree ethereum-contract vivado yocto embedded-linux uboot versal xrt libgpiod cortex-a72 amd-xilinx xcve2302 vd100 system-device-tree aie-ml zocl

Updated Apr 14, 2026

PabloSoage / scanner64

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Real-time multichannel Digital Down-Converter (DDC) bank in Verilog for AMD Kria KV260 FPGA programmable logic

real-time fpga dsp rtl verilog xilinx sdr vivado ddc fixed-point digital-signal-processing hardware-acceleration zynq-ultrascale amd-xilinx kria-kv260 cic-filter

Updated Sep 16, 2026
Verilog

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