cic-filter

Here are 7 public repositories matching this topic...

Fixed-point CIC decimator modeled for an 8-bit MCU, with bit-exact verification and frequency-domain analysis.

c embedded dsp fixed-point decimator cic-filter

A synthesizable, multi-rate 1-Bit Delta-Sigma to 36-Bit CIC Decimation Filter implemented in Verilog and verified on a Xilinx Artix-7 (Basys 3) FPGA.

asic fpga dsp verilog vivado mixed-signal artix-7 rtl-design delta-sigma cic-filter

SDR FM receiver chain in SystemVerilog - CORDIC NCO+mixer, CIC and FIR decimation, FM discriminator; bit-exact golden model end to end

fpga dsp sdr ddc systemverilog fm cordic cocotb cic-filter

Real-time multichannel Digital Down-Converter (DDC) bank in Verilog for AMD Kria KV260 FPGA programmable logic

real-time fpga dsp rtl verilog xilinx sdr vivado ddc fixed-point digital-signal-processing hardware-acceleration zynq-ultrascale amd-xilinx kria-kv260 cic-filter

Simulink-модель DDC для GSM-приёмника: NCO, перемножитель, каскад CIC/CIC-компенсатор/FIR, сравнение single и fixdt(1,16,14)

signal-processing dsp matlab simulink gsm fixed-point digital-signal-processing fir-filter cic-filter

数字升降采样器自动设计工具

fpga eda rtl verilog digital-signal-processing hardware-design pyqt6 ai-agent llm cic-filter

基于 ZYNQ 的 PDM 麦克风阵列 UDP 音频流项目（FPGA + PC 上位机）

audio fpga zynq udp verilog pcm vivado ethernet modelsim pdm rgmii cic-filter

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