#
zynq
Here are 71 public repositories matching this topic...
Xilinx Virtual Cable Server for Raspberry Pi
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Mar 14, 2022 - C
Embedded firmware for ham radio transceivers
zynq stm32 ham-radio sdr altera hdmi bare-metal baremetal hamradio allwinner ssb cortex-a53 cortex-a7 ehci stm32mp1 sdr-radio t113-s3 cortex-a55 cortex-a76
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Sep 23, 2026 - C
Simple, zero-copy DMA to/from userspace.
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Jul 18, 2023 - C
A SoC implementation of a PDP-8/I for the PiDP-8/I console
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May 29, 2026 - C
Xilinx Zynq SoC based all-in-one quadrocopter flight controller. Stereo 720p side-by-side digital video transmission.
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Mar 10, 2021 - C
Real-Time Operating System (RTOS) for Xilinx Zynq-7000 Cortex-A9 (ARMv7-A) multi-core SoCs (ZedBoard, PicoZed, MicroZed and similars) based on the ARINC 653 Part 1 specification
arm zynq xilinx cortex cortex-a zynq-7010 xilinx-vivado arinc zynq-7000 arinc653 cortex-a9 zynq-7020 z7-lite
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Aug 10, 2023 - C
ILI9488 TFT SPI display library for Xilinx SoC and FPGA
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Sep 13, 2025 - C
HLS SHA-3 Accelerator
c fpga zynq cpp verilog research-tool vivado hardware-acceleration high-level-synthesis vivado-hls vivado-ip-integrator
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Nov 25, 2018 - C
SideLine is a novel power side-channel vector based on delay-line components widely implemented in high-end SoC.
aes zynq attack hardware openssl delay remote rsa side-channel delay-line sideline delay-locked-loop
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Mar 25, 2021 - C
This framework was part of the Diploma thesis titled "Architectures and Implementations of the Neural Network LeNet-5 in FPGAs". The main goal of this thesis was to create a LeNet-5 implementation in an FPGA development board, but also form a reusable framework/workflow which can be modified to model and develop other Neural Networks as well.
machine-learning zynq keras neural-networks hardware-acceleration ristretto vivado-hls lenet-mnist fpga-programming
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Nov 16, 2025 - C
UltraZed Development
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Mar 16, 2018 - C
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