Verilog HDL implementation of the GOST R34.12-2015 — a fresh Russian government standard symmetric key block cipher.

fibonacci number calculator written in Verilog-HDL

Digital Systems Laboratory UIUC FA 2016

Design MMU for socfpga-linux 4.11. Test with Altera DE2-115.

A 32-bit RISC processor built in Verilog for CS 3220 Spring 2017

A coocbook of HDL (primarily Verilog) modules

fprga and rtos project

Dottori-Kun for FPGA

Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface

Trabalhos da matéria Sistemas Digitais UFFS 2017

OAC (Organization and Architecture of Computers) laboratories.

Hardware Accelerator for AES 128-bit Encryption and Decryption implemented (in Verilog) in Altera's FPGA board.

Uses the D8M camera module, then processes the image to detect red objects, and then overlay an x,y crosshair on the largest red object. See the video. Pure Verilog. (No soft-core processor.)

FPGA paramatized mandelbrot generator. I have tested instantiating 4, 8, and 12 calculating engines. It has a built-in VGA controller (at 640x480) with internal dual-port RAM as the frame buffer. With 4 engines it runs at 100 MHz (5 frames/sec). With 12 engines, at 112 MHz, it hits 20.5 frames/sec.

Getting started with Altera FPGA using Quartus Prime Lite17.1

The fpga project for openFPGAdunino

Video streaming from a camera to a 58x24 pixel flipdot display. See the two flipdot_display*.mp4 videos. All processing in Verilog RTL (no softcore uP).

Student-project

The logic files of SG1 project