🐙 A CAL Dataflow Compiler for High-Level Synthesis

Verilog RISC Processor Design

A collection of examples and libraries using the Altera OpenCL HLS SDK

Controle de motor DC + Sensores fim de curso implementado em VHDL para o kit DE0-CV utilizado na matéria de Elementos de sistemas do 3 semestre de Engenharia da computação do Insper.

RISC-V 1 and 5-stage CPUs Described in Chisel for Implementation in an Altera FPGA

The logic files of SG1 project

Jogo implementado numa placa FPGA Altera DE2 no âmbito de Projecto de Sistemas Digitais, maioritariamente escrito em VHDL

Moon Cresta Arcade Synthesized on an Altera DE2-35 Dev Board.

Assorted Verilog that brings up different elements (VGA, Ethernet, Switches, LED, LCD, etc.) of the terasIC DE2-70 Development Board.

Nios II processor based Qsys using Altera Quartus II 18.1 using Cyclone IV FPGA EP4CE10E22C8

BASIC-52 running on Cyclone IV at 11.0592, 25 and 50 MHz. EPCS4 configuration flash. 50MHz oscillator pin 24 used. 27 MHz unused.

Examples for the Terasic DE0-nano-SOC board

This program is to assist as a toolset for OpenCl's FPGA SDK. Since the OpenCL has a certain standard and procedure of compiling and transferring mehods to the board, this tool set was written to assist in plain english.

É uma extensão para navegadores chromium que altera o papel de parede do Whatsapp web

Simple register realisation for SystemVerilog Verification

Bagman Arcade synthesized on an Altera DE2-35 Dev Board.

Hybrid Cryptography on the DE1-SoC(Intel Cycle V FGPA). Simon Cipher algorithm is implemented in software and hardware. This SoC is composed of a HPS(ARM Cortex A9 800Mhz(dual core)) coupled with Intel/Altera Cyclone V FPGA.

A coocbook of HDL (primarily Verilog) modules

Digital Systems Laboratory UIUC FA 2016