axi4

Here are 6 public repositories matching this topic...

OSVVM / AXI4

AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components

simulation vhdl verification vip tlm testbench osvvm simulation-modeling axi4 axi4-lite axi4-stream verification-component

Updated Sep 10, 2026
VHDL

airhdl / spi-to-axi-bridge

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An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.

vhdl spi systemverilog axi4

Updated Dec 6, 2023
VHDL

VHDL / Interfaces

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Interface definitions for VHDL-2019.

interface i2c vhdl uart ethernet record i2s mipi axi4 axi4-lite axi4-stream modeview

Updated May 13, 2026
VHDL

RISMicroDevices / RMM4NC30F2X

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Gemini 30F2 (30F3 variant 00) MIPS Processor for NSCSCC2022

fpga fpga-soc out-of-order mips32 high-frequency axi4 nscscc2022 nscscc2022-single

Updated Sep 21, 2022
VHDL

mnemocron / axi-perf-counter-pattern

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Performance counter to measure latency between two AXI Stream interfaces with pattern matching as trigger.

vhdl performance-analysis axi-bus axi-stream axi4 latency-analysis

Updated Aug 3, 2023
VHDL

PLC2 / PoC-Demo-Design

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AMD Vivado Demonstrator Design using The PoC Library features.

vhdl vivado example-project poc-library mpsoc axi4 axi4-lite

Updated Oct 13, 2025
VHDL

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