kuoyaoming93 / axi_uartlite_pynq Star 1 Code Issues Pull requests PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx python jupyter-notebook xilinx uart pynq pynq-hardware-overlay xilinx-vivado axi pynq-z1 xilinx-zynq pynq-z2 Updated May 1, 2020 Tcl
kuoyaoming93 / sem-ip_pynq Star 11 Code Issues Pull requests SEM (Soft Error Mitigation) IP adapted for PYNQ-Z2 python zynq jupyter-notebook xilinx uart pynq pynq-hardware-overlay xilinx-fpga icap xilinx-vivado axi pynq-z1 pynq-z2 soft-error sem-ip Updated May 1, 2020 Tcl
ChanonTonmai / AXI-UART-very-lite Star 3 Code Issues Pull requests VHDL UART Module with AXI interface fpga xilinx uart axis axi Updated Feb 16, 2021 Tcl
MatthieuMichon / fpga-jtag-axi-demo Star 5 Code Issues Pull requests Basic JTAG / AXI demonstration on Xilinx's FPGA. fpga tcl xilinx vivado systemverilog jtag axi Updated Apr 22, 2021 Tcl
suoglu / AXI-GPIO Star 2 Code Issues Pull requests Custom AXI GPIO core with up to 32 input and 32 output ports gpio fpga axi Updated Aug 3, 2023 Tcl
d953i / Custom_Part_Data_Files Star 39 Code Issues Pull requests Discussions Xilinx PCIe to MIG DDR4 example designs and custom part data files csv fpga ddr tcl calibration verilog xilinx vivado mig axi sqrl ddr4 vcu1525 bcu1525 dimm udimm rdimm sodimm Updated Feb 4, 2024 Tcl
mwrnd / innova2_xcku15p_ddr4_bram_gpio Star 19 Code Issues Pull requests XDMA PCIe to DDR4 and GPIO and BRAM for the Innova-2 Flex XCKU15P FPGA fpga vivado pcie axi ddr4 xdma innova2 xcku15p mnv303212a innova-2-flex mnv303212a-adlt 4xc7a16683 01pg974 pcie-xdma Updated Mar 7, 2024 Tcl