bfloat16

Here are 4 public repositories matching this topic...

Essenceia / Systolic_Array_with_DFT_v2

IHP 130nm ASIC tapeout of a 2x2 bfloat16 matrix matrix multiplication with DFT infrastructure. Iteration on the previous accelerator taped out on GF180.

asic rtl verilog ihs systolic-arrays bfloat16 bfloat 130nm sg13g2 ihp-sg13g2

Updated Jul 10, 2026
Verilog

Essenceia / BFloat16

Star

RTL implementation of a performance/area optimized bfloat16 adder and multiplication.

asic verilog floating-point adder multiplier bfloat16 bf16

Updated Mar 28, 2026
Verilog

Essenceia / Teapot

Star

100Mbps Ethernet accelerator wrapper.

asic ethernet bfloat16

Updated Jul 22, 2026
Verilog

ShayanKhoshkeifi / Newton-Raphson-FPGA

Star

Verilog implementation of a Newton-Raphson floating-point compute unit on the Intel MAX10 FPGA supporting reciprocal, square root, division, and natural logarithm in bfloat16 format.

fpga verilog modelsim newton-raphson quartus-prime digitaldesign bfloat16 fixed-point-arithmetic

Updated Sep 15, 2026
Verilog

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