CPU Design project for the course "Application and Design of Digital Logic" at Glasgow College, UESTC .
-
Updated
Nov 23, 2024 - VHDL
#
fsm
A finite-state machine (FSM), finite-state automaton (FSA), or simply state machine is a mathematical model of computation and an abstract machine that can be in exactly one of a finite number of states at any given time.
The FSM can change from one state to another in response to some inputs; the change from one state to another is called a transition.
An FSM is defined by a list of its states, its initial state, and the inputs that trigger each transition.
In computer science, FSM are widely used in modeling of application behavior (control theory), design of hardware digital systems, software engineering, compilers, network protocols, and computational linguistics.
Here are 42 public repositories matching this topic...
💻 Repositório para Disciplina EEL5105 - Circuitos e Técnicas Digitais - UFSC
language counter fsm register digital hardware clock timer machine vhdl circuits description sequential multiplexer techniques quartus flip-flop multisim latch combinational
-
Updated
Apr 3, 2020 - VHDL
VHDL codes for 8-bit Vending Machine Processor, support for two drinks & three types of coins. contains: fsm, Accumulator, comparator, subtractor, mux, Adder, etc.
fsm fpga processor vhdl mux vendingmachine comparator accumulator vending-machine vhdl-code full-adder
-
Updated
Jul 20, 2021 - VHDL
Signed / unsigned multiplier / divider used by a microcode-driven prime number generator
-
Updated
Apr 7, 2018 - VHDL
Simple calculator implemented in VHDL using FSM logic
-
Updated
Aug 24, 2019 - VHDL
Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.
fsm vhdl intel finite-state-machine quartus-prime vga-driver vga-controller altera-fpga vhdl-coursework quartus2 altera-de1
-
Updated
Feb 7, 2023 - VHDL
VHDL Implementation of Modulo2 Line by Matrix Multiplication (with Tutorial Series on Steemit)
c fsm vhdl multiplication accumulator multiplication-algorithm control-signals modulo2 hardware-design
-
Updated
Oct 19, 2020 - VHDL
Finite-State Machine Design of a Simple Car Security Alarm on FPGA
-
Updated
Feb 6, 2020 - VHDL
Final project of Logical Networks course - Politecnico di Milano 2022/23
-
Updated
Sep 8, 2023 - VHDL
Projekt (UART přijímací část) z předmětu Návrh číslicových systémů (INC), druhý semestr bakalářského studia BIT na FIT VUT/BUT, ak.rok 2021/2022
fsm fpga vhdl university-project xilinx uart xilinx-fpga vutbr vut vhdl-code vut-fit vhdl-coursework uart-receiver brno-university-of-technology
-
Updated
Jan 12, 2024 - VHDL
A modular, synthesizable elevator control system implemented in VHDL with configurable floor count, request handling, FSM-based control, and 7-segment display output for FPGA implementation
-
Updated
Jan 27, 2026 - VHDL
FPGA implementation of SPI with BMP580 sensor and EEPROM memory using VHDL on ARTY S7-25
-
Updated
Mar 3, 2026 - VHDL
Flappy Bird VHDL
-
Updated
Jan 11, 2022 - VHDL
4-bit calculator with all operations we set up for calculator. It have some main parts which are FSM(Finite State Machine) which has MOP(Micro-operations). Datapath that includes calculator's brain which is ALU(Arithmetic Logic Unit), multiplexers and hexadecimal decoder.
-
Updated
Oct 22, 2023 - VHDL
FSM and Cache design for practicing the concepts of computer architecture
-
Updated
May 1, 2021 - VHDL
This project implements a complete UART communication system in VHDL, where a transmitter sends serial data, a receiver reconstructs it using mid-bit sampling, and a testbench automatically verifies correctness using simulation and waveforms.
-
Updated
Jan 27, 2026 - VHDL
Prova Finale di Reti Logiche - Polimi Ingegneria Informatica - A.A. 2019-2020
-
Updated
Oct 11, 2020 - VHDL
- Followers
- 31 followers
- Website
- github.com/topics/finite-state-machine
- Wikipedia
- Wikipedia