Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.

This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.

Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1

Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis

A hardware implementation of a deep learning accelerator using SystemVerilog/Verilog, designed for efficient neural network inference. This project implements a systolic array-based matrix multiplication unit with various activation functions and supporting components.

A Deep Neural Network-inference accelerator is created in hardware. The codes for hardware is written in System Verilog. The hardware module is interfaced with NIOS computer system, thus this hardware acts as a peripheral to the computer system. The driver code to interface the hardware is written in C. Speedup compard to software is 400 times.

This is the hardware description of the OpenTPU Project. This simulator allows anyoneto test performance of tpu on their own computer and explore hardware acceleration

A FIPS 202 compliant SystemVerilog implementation of the Keccak permutation (SHA-3/SHAKE). Features a high-frequency multi-cycle architecture, runtime-configurable modes (SHA3-256/512, SHAKE128/256), and standard AXI4-Stream interfaces with full backpressure support. Verified using embedded SVA properties and official NIST test vectors.

Verilog implementation of a parameterized systolic array for square matrix multiplication. Includes 2×2, 3×3, and 4×4 test cases, simulation logs, and full documentation.