The Task Parallel System Composer (TaPaSCo)
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Dec 19, 2025 - Verilog
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hardware-acceleration
Here are 29 public repositories matching this topic...
XCrypto: a cryptographic ISE for RISC-V
open-source cryptography cpu crypto hardware riscv verilog research-project mit-license ise icarus-verilog hardware-acceleration formal-verification yosys instruction-set-architecture risc-v xcrypto
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Jan 5, 2023 - Verilog
Hardware accelerator for convolutional neural networks
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Aug 9, 2022 - Verilog
[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
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Mar 30, 2021 - Verilog
This project is being developed as part of a Master's degree research sponsored by Brazil's CNPQ. It's goal is to design a hardware architecture to accelerate the AV1 arithmetic encoder.
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Oct 4, 2022 - Verilog
Real-Time Hardware Sorter, Using A Multi-Dimensional Sorting Algorithm
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Apr 27, 2023 - Verilog
This repository contains the design and implementation of a Spiking Neural Network (SNN) Processor. Spiking Neural Networks are a biologically-inspired class of artificial neural networks, where neurons communicate by sending discrete spikes.
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Oct 19, 2024 - Verilog
grayscale conversion system and simple convolution system
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Aug 25, 2021 - Verilog
Gravitational simulation of the N-body problem using FPGA hardware acceleration
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May 12, 2018 - Verilog
Welcome to the repository for **Exercise 3 of the AI Systems Course** at the **University of Tehran**. This project focuses on designing and implementing a lightweight, efficient **processing element (PE)** for performing operations of neurons in a **multi-layer perceptron (MLP)** using Verilog.
fpga neural-network verilog mlp hardware-acceleration ai-systems fpga-programming processing-element
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May 5, 2025 - Verilog
MFCC Core written in SystemVerilog
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Oct 22, 2025 - Verilog
sequence detector with overlapped 2 patterns 010111 or 1101
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Aug 25, 2021 - Verilog
Hardware recreation of Atari Breakout on an FPGA using SystemVerilog and VGA graphics. Includes FSMs, real-time collision logic, and memory-mapped display.
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Jul 14, 2025 - Verilog
High-performance FAST Corner Detector on PYNQ with using Hardware Acceleration (80+ FPS).
opencv computer-vision fpga hardware image-processing verilog vivado hardware-designs slam pynq hardware-acceleration codesign slam-algorithms orbslam hardware-accelerator orbslam3 zynq-ultrascale fast-corner-detector hardwaresoftware
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Dec 17, 2025 - Verilog
The IPPro is a 16-bit signed fixed-point, five-stage balanced pipelined RISC architecture that exploits the DSP48E1 features and provides balance among performance, latency and efficient resource utilization.
fpga processor image-processing microprocessor datapath risc hardware-acceleration softcore xilinx-zynq pipelined-processors ippro
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Feb 14, 2023 - Verilog
Specialized FPU for Fast Inverse Square Root Algorithm
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Nov 10, 2022 - Verilog
Hardware accelerator for comparing molecule fingerprints.
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Oct 21, 2025 - Verilog
A minimal FPGA accelerator kernel for hyperdimensional computing (HDC) inference
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Dec 17, 2025 - Verilog
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