High-performance FAST Corner Detector on PYNQ with using Hardware Acceleration (80+ FPS).

A Custom Hardware Accelerator for Image Segmentation Using U-Net for Autonomous Driving Applications

MFCC Core written in SystemVerilog

grayscale conversion system and simple convolution system

This project implements a neuromorphic Network-on-Chip using customized RV32IMF RISC-V cores, a 2D mesh NoC, and neuron bank hardware to accelerate spiking neural networks. It supports event-driven spike communication via custom ISA extensions and AXI interfaces, and is implemented and tested on an FPGA.

Verilog implementation of an ordinary differential equation (ODE) solver accelerator chip ― **INCOMPLETE IMPLEMENTATION**

🚀 Implement a high-performance FAST corner detector on the PYNQ platform, leveraging FPGA for efficient feature extraction and real-time data visualization.

Hardware acceleration of image scaling

Welcome to the repository for **Exercise 3 of the AI Systems Course** at the **University of Tehran**. This project focuses on designing and implementing a lightweight, efficient **processing element (PE)** for performing operations of neurons in a **multi-layer perceptron (MLP)** using Verilog.

sequence detector with overlapped 2 patterns 010111 or 1101

A minimal FPGA accelerator kernel for hyperdimensional computing (HDC) inference

Matrix Multplication in hardware (verilog), for efficiently computing matrix products on an FPGA DE-10 Lite board. This efficient architcture implimenting a 8x8 systollic array can compute a product in 75% less clock cycles than a modern CPU

This project implements a neuromorphic NoC using RISC-V nodes with custom hardware to simulate spiking neural networks. Tested on an FPGA, it supports up to 1,024 neurons and uses dedicated FIFO buffers for stable, low-power operation. The design combines RISC-V flexibility with hardware acceleration for efficient small-scale SNN applications.

Computer Organisation Project for EE2003

Hardware recreation of Atari Breakout on an FPGA using SystemVerilog and VGA graphics. Includes FSMs, real-time collision logic, and memory-mapped display.

The IPPro is a 16-bit signed fixed-point, five-stage balanced pipelined RISC architecture that exploits the DSP48E1 features and provides balance among performance, latency and efficient resource utilization.

It is the CORDIC implementation in Verilog. CORDIC is a hardware algorithm (CORDIC 硬體演算法) based on simple additions/subtractions and bit shifts. It can compute trigonometric, hyperbolic, exponentials, logarithms, multiplication, division, square, and square-root. And it is widely used in digital signal processing (DSP), embedded systems and FPGAs.

Specialized FPU for Fast Inverse Square Root Algorithm

Gravitational simulation of the N-body problem using FPGA hardware acceleration

This repository contains the design and implementation of a Spiking Neural Network (SNN) Processor. Spiking Neural Networks are a biologically-inspired class of artificial neural networks, where neurons communicate by sending discrete spikes.