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hardware-acceleration

Here are 31 public repositories matching this topic...

esa-tu-darmstadt / tapasco

The Task Parallel System Composer (TaPaSCo)

fpga hardware hardware-acceleration fpga-soc

Updated Jan 28, 2026
Verilog

GraphSAINT / GNN-ARCH

[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)

fpga accelerator hardware-acceleration gcn graphsage

Updated Mar 30, 2021
Verilog

scarv / xcrypto

XCrypto: a cryptographic ISE for RISC-V

open-source cryptography cpu crypto hardware riscv verilog research-project mit-license ise icarus-verilog hardware-acceleration formal-verification yosys instruction-set-architecture risc-v xcrypto

Updated Jan 5, 2023
Verilog

8krisv / CNN-ACCELERATOR

Hardware accelerator for convolutional neural networks

cnn verilog convolutional-neural-networks computer-architecture hardware-acceleration

Updated Aug 9, 2022
Verilog

amin-norollah / RTHS

Real-Time Hardware Sorter, Using A Multi-Dimensional Sorting Algorithm

fpga high-performance verilog sorting-algorithms hardware-acceleration sorting-network

Updated Jan 4, 2026
Verilog

tuliopereirab / arithmetic-encoder-av1

This project is being developed as part of a Master's degree research sponsored by Brazil's CNPQ. It's goal is to design a hardware architecture to accelerate the AV1 arithmetic encoder.

hardware hardware-designs hardware-acceleration arithmetic-coding av1 entropy-coding

Updated Oct 4, 2022
Verilog

acsl-technion / flexdriver-zuc

FlexDriver ZUC cipher example AFU.

crypto fpga hardware-acceleration zuc eea3 eia3

Updated Dec 21, 2021
Verilog

gustavomotadev / engg57-ransac

Application of the RANSAC algorithm in embedded C and Verilog for Altera Nios II and Cyclone IV E.

c fpga verilog hardware-designs ransac hardware-acceleration fpga-programming ransac-algorithm

Updated Dec 3, 2020
Verilog

abdelazeem201 / Spiking-Neural-Processor

This repository contains the design and implementation of a Spiking Neural Network (SNN) Processor. Spiking Neural Networks are a biologically-inspired class of artificial neural networks, where neurons communicate by sending discrete spikes.

asic fpga rtl neuromorphic hardware-acceleration fpga-accelerator

Updated Oct 19, 2024
Verilog

briansune / FFT-R22SDF

R22SDF FFT VLSI/FPGA investigate and implementation

fpga verilog xilinx fft vlsi hardware-acceleration

Updated Apr 22, 2022
Verilog

acsl-technion / flexdriver-iot-auth

FlexDriver IoT authentication offload example AFU.

coap fpga json-web-token hardware-acceleration hmac-sha256

Updated Dec 21, 2021
Verilog

mozerj2001 / fp_accel

Hardware accelerator for comparing molecule fingerprints.

fpga fingerprint hardware-acceleration pharmacophore vitis

Updated Oct 21, 2025
Verilog

fsiddiqui85 / IPPro

The IPPro is a 16-bit signed fixed-point, five-stage balanced pipelined RISC architecture that exploits the DSP48E1 features and provides balance among performance, latency and efficient resource utilization.

fpga processor image-processing microprocessor datapath risc hardware-acceleration softcore xilinx-zynq pipelined-processors ippro

Updated Feb 14, 2023
Verilog

JasonHsiao8 / Cordic-hardware-algorithm-implementation-and-application

It is the CORDIC implementation in Verilog. CORDIC is a hardware algorithm (CORDIC 硬體演算法) based on simple additions/subtractions and bit shifts. It can compute trigonometric, hyperbolic, exponentials, logarithms, multiplication, division, square, and square-root. And it is widely used in digital signal processing (DSP), embedded systems and FPGAs.

algorithms hardware ics hardware-designs hardware-acceleration cordic ic-design low-cost cordic-algorithm hardware-algorithms

Updated Jan 7, 2026
Verilog

dyna-bytes / FISR

Specialized FPU for Fast Inverse Square Root Algorithm

verilog floating-point hardware-acceleration fpu

Updated Nov 10, 2022
Verilog

scott0123 / GravSim

Gravitational simulation of the N-body problem using FPGA hardware acceleration

fpga simulation physics-simulation hardware-acceleration nios-ii nbody-problem

Updated May 12, 2018
Verilog

ashs810061 / Design-and-Implementation-of-an-Energy-Efficient-FAST-Corner-Detection-Accelerator-on-PYNQ

High-performance FAST Corner Detector on PYNQ with using Hardware Acceleration (80+ FPS).

opencv computer-vision fpga hardware image-processing verilog vivado hardware-designs slam pynq hardware-acceleration codesign slam-algorithms orbslam hardware-accelerator orbslam3 zynq-ultrascale fast-corner-detector hardwaresoftware

Updated Dec 17, 2025
Verilog

yasith46 / self_driving_unet_custom_ip

A Custom Hardware Accelerator for Image Segmentation Using U-Net for Autonomous Driving Applications

ip hardware-designs unet hardware-acceleration

Updated Dec 2, 2025
Verilog

Unicamp-Odhin / MFCC_Core

MFCC Core written in SystemVerilog

audio fpga dsp verilog systemverilog mfcc hardware-acceleration audio-processing

Updated Jan 28, 2026
Verilog

HsuChiChen / ncku-intro-vlsi

grayscale conversion system and simple convolution system

convolutional-neural-networks hardware-acceleration hspice grayscale-image-converter vlsi-cad

Updated Aug 25, 2021
Verilog

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