ISA tools API

✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.

A 16-bit RISC-V Inspired ISA

AltamISA: a Python API for ISA-Tab files

Implementation of Custom Simulator and Assembler for a hypothetical Instruction Set Architecture along with Visualization for Memory Access Location over Time

A strange little 16bit ISA

A 64-bit stack based instruction set architecture definition with reference implementation. (The assembler is part of my C compiler that targets StackVM)

Instruction database extracted from LLVM source

An assembler and ISA simulator for the RISC-V assembly language.

RAG powered tool that answers technical questions about the official RISC-V ISA

An 8-bit CPU Instruction Set Architecture (ISA), designed for Minecraft redstone computers.

A hands free method to fill out the TRAQ form. Evaluators spend alot of time on the road, often in locations with no cellular service.

El presente repositorio tiene como objetivo principal tener un control de versiones para el Primer Proyecto Grupal del curso de Arquitectura de Computadores I (CE4301) del Instituto Tecnológico de Costa Rica

🧮 Converts hexadecimal input to risc instruction

ANSI/ISA 5.1 Decoder for python

asi, the fictitious isa

RISC-V Opcodes for the Unlimited Vector Extension

MVP platform to match students and investors via ISAs – FinTech Assignment @ RSM

A Python-based assembler for a custom 16-bit processor. Converts assembly syntax into 20-bit aligned binary machine code compatible with Verilog $readmemb initialization.

an isa, compiler for the isa, and supporting graphs for a desmos-based computer