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nxbyte / ARM-LEGv8

Verilog Implementation of an ARM LEGv8 CPU

arm verilog xilinx isa vivado hazard-detection ldr pipeline-cpu single-cycle hennessy patterson legv8-arm multi-cycle arm-legv8-simulator forwarding-unit

Updated Oct 3, 2018
Verilog

nukeykt / LPC-Sound-Blaster

Star

FPGA Sound Blaster over LPC bus experiments

isa lpc adlib opl ymf262 opl3 soundblaster sound-blaster

Updated Dec 3, 2023
Verilog

alexfru / SediCiPC

Star

16-bit PC based on SediCiPUv2 CPU

Updated Apr 5, 2026
Verilog

Pranav-2045 / rv32i-single-cycle-core

Star

Hardware-synthesizable RV32I single-cycle core in strict Verilog-2001, modeled after Harris & Harris. Implemented on Artix-7 (125 MHz) with dual-port LUTRAM regfile, zero timing violations, and an interactive schematic viewer.

Updated Jul 29, 2026
Verilog

grachale / microarchitecture_RISC_V

Star

Design of a Processor Microarchitecture Supporting a Chosen Subset of RISC-V ISA Instructions.

assembly verilog isa risc-v microarchitecture

Updated Aug 6, 2023
Verilog

Bengal1 / MIPS-32-Microprocessor-Verilog

Star

Reduced MIPS 32-bit Processor

mips verilog isa verilog-hdl

Updated Aug 17, 2026
Verilog

captaindane / swt16

Star

A 16-bit, 5-stage RISC processor. RTL description in Verilog. Includes assembler, simulator, and example programs.

simulation processor assembler verilog isa risc 16-bit 5-stage-pipeline rtl-description

Updated Feb 5, 2020
Verilog

bimalka98 / DownSampleMe

Star

A custom processor implemented in Verilog HDL for image down sampling for UOM's EN3030 Circuits and Systems Design module ❄

fpga image-processing verilog isa assembly-language-programming xilinx-vivado downsampling micro-instructions custom-processor control-lut

Updated Jul 14, 2022
Verilog

Conor-Mc-Ardle / Risk-V-Processor-Verilog-

Star

Finished. Plans to pipeline and implement on fpga in future. NTS - Push immediate gen update for default case.

students custom verilog isa student-project verilog-hdl instruction-set-architecture risc-v riscv32 verilog-simulator verilog-project verilog-code

Updated Jul 23, 2026
Verilog

harshalmittal4 / 24-bit-RISC-Processor

Star

Computer Architecture-MIPS Processor simulation in verilog with self developed ISA

verilog isa risc-processor

Updated Aug 25, 2019
Verilog

icarotelesdasilva / DestByte8

Star

my prototype cpu, real hardware, custom architecture., a real own architecture CPU hardware.

cpu verilog isa low-level cpu-monitoring cpu-emulator low-code cpu-scheduling cpu-inference

Updated Sep 13, 2026
Verilog

satgupta23 / verilog-32-bit-processor

Star

Single-cycle 32-bit RISC-V processor in Verilog implementing core RV32I and the full RV32M extension, with a custom datapath, control unit, memory subsystem, and automated 92-checkpoint verification in AMD Vivado.

vhdl verilog isa vivado riscv32 fpga-programming

Updated Aug 7, 2026
Verilog

BradDevicesOfficial / BradISA

Star

BradISA — the Brad Devices CPU instruction set architecture: the shared software contract behind every BradCore (Phoenix P-cores, Falcon E-cores), with Verilog/VHDL reference cores

cpu vhdl rtl verilog isa risc reference-implementation instruction-set bradverse bradisa

Updated Sep 21, 2026
Verilog

jwolak / BorussCPU-Laibach

Star

BorussCPU "Laibach" is an experimental 8-bit RISC processor designed in Verilog. The project aims to demonstrate the complete process of CPU design, from architecture and implementation to verification with unit, integration tests and a dedicated assembly compiler BorASM

cpu fpga rtl verilog isa educational hardware-designs computer-architecture 8bit digital-design risc-processor 8-bit-cpu cpu-design risc-architecture custom-cpu

Updated Jul 23, 2026
Verilog

viv27 / RTL_Toolchain

Star

Python toolchain that autogenerates synthesizable Verilog RTL from a JSON ISA specification control unit decoder, ROM based control unit, and testbench for a custom 16-bit processor ISA.

python toolchain hardware architecture computer rtl verilog isa iverilog

Updated May 20, 2026
Verilog

JaafarRammal / Jafadrian-ISA

Star

A custom RISC 16-bit CPU running at 50MHz on an FPGA

fpga assembly verilog isa risc

Updated Jan 12, 2020
Verilog

Melis710 / mips-single-cycle-processor-design

Star

A 32-bit MIPS ISA single-cycle processor design, implemented in Verilog.

mips verilog isa digital-logic computer-architecture processor-design cpu-design

Updated Feb 18, 2026
Verilog

jwolak / Arina-4

Star

A 4-bit accumulator-based microprocessor inspired by the Intel 4004 architecture.

fpga rtl verilog isa educational hardware-designs computer-architecture risc digital-design 4-bit processor-design cpu-design 4-bit-cpu custom-cpu

Updated Jul 14, 2026
Verilog

markelmencia / LITE-16

Star

A 16-bit Instruction Set Architecture.

assembly verilog isa 16-bit risc-v

Updated Oct 24, 2025
Verilog

BradDevicesOfficial / BradVector

Star

BradVector — the Brad Devices GPU/accelerator ISA: spec, reference RTL, and toolchain

toolchain gpu assembly wasm isa instruction-set-architecture simt bradvector bradverse reference-rtl

Updated Sep 20, 2026
Verilog

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Here are 21 public repositories matching this topic...

nxbyte / ARM-LEGv8

nukeykt / LPC-Sound-Blaster

alexfru / SediCiPC

Pranav-2045 / rv32i-single-cycle-core

grachale / microarchitecture_RISC_V

Bengal1 / MIPS-32-Microprocessor-Verilog

captaindane / swt16

bimalka98 / DownSampleMe

Conor-Mc-Ardle / Risk-V-Processor-Verilog-

harshalmittal4 / 24-bit-RISC-Processor

icarotelesdasilva / DestByte8

satgupta23 / verilog-32-bit-processor

BradDevicesOfficial / BradISA

jwolak / BorussCPU-Laibach

viv27 / RTL_Toolchain

JaafarRammal / Jafadrian-ISA

Melis710 / mips-single-cycle-processor-design

jwolak / Arina-4

markelmencia / LITE-16

BradDevicesOfficial / BradVector

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