Game of Balance is an accelerometer based maze navigation game, with added features of score and life, that is built on Nexys 4 DDR development board.
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Jan 27, 2018 - VHDL
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microblaze
Here are 15 public repositories matching this topic...
A series of projects using the floating point division IP from Xilinx to perform floating point (single precision) division. Boards used: ZYBO and NEXYS4DDR (ARTIX-7)
c sdk fpga zynq verilog xilinx floating-point hdl division xilinx-vivado microblaze zynq-7000 nexys4ddr floating-ip artix-7 floating-point-conversion
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Apr 5, 2022 - VHDL
FPGA benchmark of vectorized gradient descent on linear regression
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Mar 27, 2026 - VHDL
VHDL implementation of SHA-256. Reconfigurable Computing course
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Jan 29, 2019 - VHDL
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
design communication-protocol pipeline digital hardware electronics signal-processing processor master-slave verilog fft vivado intellectual-property c-programming integrated-circuits microblaze axi interconnect microelectronics vitis
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Apr 13, 2024 - VHDL
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
design fpga communication-protocol digital hardware electronics processor master-slave verilog vivado floating-point intellectual-property c-programming integrated-circuits microblaze axi interconnect microelectronics vitis arty-s7
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Apr 13, 2024 - VHDL
Fibonacci implementation for FPGA (in VHDL) and for Microblaze processor for FPGA (in C)
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Jan 19, 2019 - VHDL
Personal FPGA Proyects mostly Xilinx / Vivado and Some Multisim
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Aug 17, 2018 - VHDL
Temple Run–style 2.5D endless runner implemented on an FPGA with a MicroBlaze SoC, custom renderer IP, and HDMI framebuffer controller.
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Jan 10, 2026 - VHDL
FPGA based Embedded Systems module assignment
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Nov 27, 2016 - VHDL
International Data Encryption Algorithm implementation for FPGA (in VHDL) and Microblaze processor for FPGA (in C)
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Jan 19, 2019 - VHDL
UVM based Verification of SPI_Protocol and I2C_Protoccol. A Serial intra System Communication Peripheral Protocol
c fpga i2c verilog spi vivado systemverilog uvm verdi microblaze axi hardware-description-language basys3-fpga synopsys-vcs
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Jul 24, 2025 - VHDL
Arquitectura de Computadoras 2018-2019
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Dec 21, 2020 - VHDL
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