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This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between computer and peripherals. UART mainly contains Transmitter, Receiver and Baud Rate Generator. Baud Rate Generator generates the clock for the UART. We can achieve the desired Baud Rate by using divide factor from sys…

  • Updated Mar 30, 2022
  • Verilog

Python flask based India railway PNR status tracker This repository contains the source code for a PNR status website, a comprehensive online platform designed to provide real-time information about the status of passenger train reservations. Built using HTML, CSS, and JavaScript, this website offers a user-friendly interface with interactive fea

  • Updated Nov 7, 2025
  • HTML

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