This repository contains the final project of my Physical Design Internship at ICpedia. The goal was to implement a complete RTL-to-GDSII flow for the wbqspiflash design using the OpenROAD & OpenLane toolchain
End-to-end RTL to GDSII ASIC physical design implementation at 28nm using Synopsys DC and ICC2 with full timing closure and DRC clean signoff.
A pipelined DLX processor implemented in VHDL. Includes a 5-stage datapath with hazard and forwarding units, testbenches, a Python single-cycle emulator for fast verification, and a fully automated physical implementation flow.
Python flask based India railway PNR status tracker This repository contains the source code for a PNR status website, a comprehensive online platform designed to provide real-time information about the status of passenger train reservations. Built using HTML, CSS, and JavaScript, this website offers a user-friendly interface with interactive fea
A web-based Verilog simulator for designing, running, and visualizing RTL code in-browser.
4-bit serial multiplier implementation in Verilog HDL with Moore FSM control. Features serial I/O conversion, comprehensive synthesis analysis, and complete design documentation including timing analysis and place-and-route results.
A smart platform to help last-minute train ticket seekers connect with those looking to cancel their bookings — enabling secure, verified, and seamless ownership transfers.
This repository contains my BSc graduation project at the Faculty of Engineering, Ain Shams University. The project focuses on implementing the RISC-V core, specifically the CV32E40 ,with a focus on achieving high performance and maximizing frequency through synthesis, place and route (PNR).
This repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II
My Graduation Project for BSc of Engineering Ain Shams Uni which is ASIC implementation of PULPino SoC based on the cv32e40p (RISCY) core sponserd by ICpedia using Synopsys tools
RTL to GDSII flow of a low Power configurable multi clock digital system
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