YosysHQ / picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
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PicoRV32 - A Size-Optimized RISC-V CPU
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
HDL libraries and projects
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket
The USRP™ Hardware Driver Repository
OpenSTA engine
Submission template for Tiny Tapeout SKY130 (ChipFoundry) shuttles - Verilog HDL Projects
Verilog Ethernet components for FPGA implementation
Low cost microcontroller + FPGA board for makers , hobbyist and student for endless possibility.
An Open-source FPGA IP Generator