alexforencich / verilog-ethernet
Verilog Ethernet components for FPGA implementation
See what the GitHub community is most excited about today.
Verilog Ethernet components for FPGA implementation
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
PicoRV32 - A Size-Optimized RISC-V CPU
HDL libraries and projects
RTL, Cmodel, and testbench for NVDLA
Wraps the NVDLA project for Chipyard integration
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
The Ultra-Low Power RISC-V Core
Verilog PCI express components
An Open-source FPGA IP Generator
FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket