pulp-platform / axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Official repository of the AWS EC2 FPGA Hardware and Software Development Kit
Common SystemVerilog components
HW Design Collateral for Caliptra RoT IP
VeeR EL2 Core
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.