lowRISC / opentitan
OpenTitan: Open source silicon root of trust
See what the GitHub community is most excited about today.
OpenTitan: Open source silicon root of trust
BaseJump STL: A Standard Template Library for SystemVerilog
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Common SystemVerilog components
A minimal GPU design in Verilog to learn how GPUs work from the ground up