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A minimal GPU design in Verilog to learn how GPUs work from the ground up
OpenTitan: Open source silicon root of trust
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
A minimal tensor processing unit (TPU), inspired by Google's TPU V2 and V1
RSD: RISC-V Out-of-Order Superscalar Processor
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
A Linux-capable RISC-V multicore for and by the world
Project F brings FPGAs to life with exciting open-source designs you can build on.
BaseJump STL: A Standard Template Library for SystemVerilog
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…
An exploration of log domain "alternative floating point" for hardware ML/AI accelerators.
Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous platforms.
CMake, SystemVerilog and SystemC utilities for creating, building and testing RTL projects for FPGAs and ASICs.
A Fast, Low-Overhead On-chip Network
A simple superscalar out-of-order RISC-V microprocessor
SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
Zama's Homomorphic Processing Unit implementation on FPGA
An AXI4 crossbar implementation in SystemVerilog
RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Accelerator
RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.
RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
Vector processor for RISC-V vector ISA