This repository extends the original RISC-V SoC into a two-die system connected a behavioral UCIe 2.0-style link

RTL for AXI over UCIe bridge.

😘 让你“爱”上 GitHub，解决访问时图裂、加载慢的问题。（无需安装）

RISC-V SoC with AXI4 crossbar, peripherals, and ML accelerators

Index of hardware design repositories — CPUs, arithmetic units, SoC design, HDL, and power electronics

Simulator code of the paper "Dissecting and Modeling the Architecture of Modern GPU Cores"

Apache NuttX is a mature, real-time embedded operating system (RTOS)

Integration of FlooNoC into the UMI chiplet framework for evaluating chiplet interconnect latency and throughput using RTL simulation.

A nice-to-have SystemVerilog-UVM verification kit

CHERI-enabled secure enclave that can be integrated as a subsytem on a system on chip.

SoC integrated using Amaratnh HDL

Unified RISC-V Access Platform project repository

Parameterized 256KB L2 Cache Controller — SystemVerilog RTL, MESI Coherency, AXI4/ACE, UVM-1.2 Testbench, JasperGold FPV, DFT Scan/BIST, Synopsys DC Synthesis, Cadence Innovus P&R

https://chipsalliance.github.io/guineveer/

WaveEye is an AXI4-Lite protocol root cause analysis tool that explains why a violation must occur by identifying missing inter-FSM dependencies and execution-order semantics in RTL.

SVDB Gateway : DPI-C library that links SystemVerilog simulations with external SQLite databases for configuration, logging, and verification.

SystemVerilog and UVM topology diagramming tool

Read chapters directly from this repo - do not use GitHub Pages link.

Repository of Nebula Core microarchitecture from Alchemist RV SoC