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Starred repositories

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Scala 57 6 Updated Feb 2, 2026

a verification platform for wujian100 open source SoC

SystemVerilog 4 2 Updated Jun 11, 2025

An configurable open-source RISC-V instruction set simulator in C++. RV32GBC_Zicsr_Zbc_Zicntr.

C++ 7 Updated Jan 20, 2026

Baochip 1x Silicon

SystemVerilog 208 14 Updated Feb 1, 2026
VHDL 4 Updated Jan 8, 2026
SystemVerilog 1 Updated Aug 17, 2025

A custom 3D graphics card inspired by the 3dfx Voodoo 1, implemented on an FPGA with PCIe interface and a Glide-style graphics API.

C++ 2 1 Updated Jan 4, 2026

Implementation of an NPU that can be integrated into a RISC- V core through X-Interface.

SystemVerilog 33 8 Updated Sep 17, 2024

CMake based hardware build system

CMake 35 6 Updated Jan 30, 2026
C++ 68 30 Updated Jun 7, 2017

RISC-V out-of-order core for education and research purposes

Python 81 21 Updated Jan 19, 2026

Rudimentary 3D GPU written in SystemVerilog for FPGA

SystemVerilog 4 2 Updated Sep 5, 2025

Console-class GPU core with ray tracing, VRS support, and 2 TFLOPs compute performance for high-end mobile gaming. SystemVerilog RTL implementation.

SystemVerilog 1 Updated Nov 2, 2025

Tensor computing core

SystemVerilog 8 2 Updated Dec 3, 2025
Verilog 2 1 Updated Nov 28, 2025
C++ 8 Updated Jan 12, 2026

Hardware implementation of a neural processing unit on PYNQ-Z2 FPGA

TeX 4 Updated Nov 14, 2025

Zama's Homomorphic Processing Unit implementation on FPGA

SystemVerilog 216 34 Updated Jan 14, 2026

UVM testbench and verification environament for GPU shader block RTL project

SystemVerilog 2 Updated Nov 20, 2025

Testbenches for HDL projects

SystemVerilog 22 23 Updated Jan 30, 2026

一种通用CNN加速器

Verilog 3 Updated Jan 16, 2026

A x86 Unix-like OS made entirely from scratch

C 274 10 Updated Oct 27, 2025

Virtual Prototype for identifying Application Specific Hardware Optimization candidates

C++ 11 2 Updated Dec 3, 2025

SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations

Verilog 17 2 Updated Jan 11, 2026

PyTorchSim is a Comprehensive, Fast, and Accurate NPU Simulation Framework

Python 89 16 Updated Feb 5, 2026

Tropic01 RTL design

SystemVerilog 13 Updated Oct 20, 2025
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