Starred repositories
a verification platform for wujian100 open source SoC
An configurable open-source RISC-V instruction set simulator in C++. RV32GBC_Zicsr_Zbc_Zicntr.
A custom 3D graphics card inspired by the 3dfx Voodoo 1, implemented on an FPGA with PCIe interface and a Glide-style graphics API.
Implementation of an NPU that can be integrated into a RISC- V core through X-Interface.
RISC-V out-of-order core for education and research purposes
Rudimentary 3D GPU written in SystemVerilog for FPGA
Console-class GPU core with ray tracing, VRS support, and 2 TFLOPs compute performance for high-end mobile gaming. SystemVerilog RTL implementation.
Hardware implementation of a neural processing unit on PYNQ-Z2 FPGA
Zama's Homomorphic Processing Unit implementation on FPGA
UVM testbench and verification environament for GPU shader block RTL project
Testbenches for HDL projects
Virtual Prototype for identifying Application Specific Hardware Optimization candidates
SystemVerilog Implementations of CUDA/TensorCore/TPU GEMM Operations
PyTorchSim is a Comprehensive, Fast, and Accurate NPU Simulation Framework