PicoRV32 - A Size-Optimized RISC-V CPU

Verilog Ethernet components for FPGA implementation

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

IC design and development should be faster，simpler and more reliable

Verilog AXI components for FPGA implementation

SERV - The SErial RISC-V CPU

The Ultra-Low Power RISC-V Core

FPGA modules used together with the PCILeech Direct Memory Access (DMA) Attack Software

RISC-V CPU Core (RV32IM)

Verilog library for ASIC and FPGA designers

OpenXuantie - OpenC910 Core

32-bit Superscalar RISC-V CPU

RISC-V XV6/Linux SoC, marchID: 0x2b

3-stage RV32IMACZb* processor with debug

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: FPGA, hardware

A tiny Open POWER ISA softcore written in VHDL 2008

synthesiseable ieee 754 floating point library in verilog

MIPS CPU implemented in Verilog

Enabling Flexible FPGA High-Level Synthesis of Tensorflow Deep Neural Networks

RISC-V Formal Verification Framework

Repository for basic (and not so basic) Verilog blocks with high re-use potential

VRoom! RISC-V CPU

A Pi emulating a GameBoy sounds cheap. What about an FPGA?

A Verilog HDL model of the MOS 6502 CPU

🌟 IceZUM Alhambra: an Arduino-like Open FPGA electronic board

FuseSoC-based SoC for VeeR EH1 and EL2

Open source implementation of a x86 processor

ao486 port for MiSTer