ultraembedded

ultraembedded

CPU designs, digital HW IP, emulation and embedded system projects

1.4k followers · 5 following

Achievements

libhelix-mp3 Public

Fixed-point MP3 decoder (RISC-V port)

mp3 risc-v

C 106 32 Other Updated Feb 23, 2024
libsigrok Public
Forked from sigrokproject/libsigrok

Read-only mirror of the official repo at git://sigrok.org/libsigrok. Pull requests welcome. Please file bugreports at sigrok.org/bugzilla.

C 8 1 GNU General Public License v3.0 Updated Nov 8, 2022
core_jpeg Public

High throughput JPEG decoder in Verilog for FPGA

fpga mjpeg verilog motion-jpeg verilog-hdl jpeg-decoder axi-stream

Verilog 255 49 Apache License 2.0 Updated Mar 5, 2022
core_enet Public

Ethernet MAC 10/100 Mbps

Verilog 31 8 Apache License 2.0 Updated Oct 31, 2021
core_spiflash Public

SPI-Flash XIP Interface (Verilog)

fpga verilog spi spi-flash xip axi4

Verilog 48 12 GNU Lesser General Public License v2.1 Updated Oct 24, 2021
core_ddr3_controller Public

A DDR3 memory controller in Verilog for various FPGAs

Verilog 560 103 Updated Oct 10, 2021
riscv Public

RISC-V CPU Core (RV32IM)

asic cpu fpga verification verilog pipeline-processor risc-v

Verilog 1,633 277 BSD 3-Clause "New" or "Revised" License Updated Sep 18, 2021
biriscv Public

32-bit Superscalar RISC-V CPU

linux asic cpu fpga verilog xilinx superscalar

Verilog 1,176 200 Apache License 2.0 Updated Sep 18, 2021
exactstep Public

Instruction set simulator for RISC-V, MIPS and ARM-v6m

mips armv6 risc-v instruction-set-simulator mips32 riscv32 riscv64

C++ 108 19 BSD 3-Clause "New" or "Revised" License Updated Sep 18, 2021
core_uriscv Public

Another tiny RISC-V implementation

Verilog 64 16 Apache License 2.0 Updated Jul 19, 2021
openFPGALoader Public
Forked from trabucayre/openFPGALoader

Universal utility for programming FPGA

C++ 4 Apache License 2.0 Updated Jul 11, 2021
cores Public

Various HDL (Verilog) IP Cores

audio asic fpga usb rtl verilog spi

Verilog 871 229 Updated Jul 1, 2021
core_dbg_bridge Public

UART -> AXI Bridge

fpga verilog uart axi4

Verilog 70 22 GNU Lesser General Public License v2.1 Updated Jul 1, 2021
openlogicbit Public

Open-source Logic Analyzer gateware for various FPGA dev boards/replacement gateware for commercially available logic analyzers.

fpga verilog logic-analyzer xilinx-fpga altera-fpga lattice-fpga digital-signal-analyzer

Verilog 160 20 Apache License 2.0 Updated Jun 24, 2021
core_ftdi_bridge Public

FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge

fpga verilog ftdi communications-blocks ftdi-232h axi4

Verilog 32 13 GNU General Public License v2.0 Updated Jun 5, 2021
core_usb_bridge Public

USB -> AXI Debug Bridge

fpga usb verilog usb-cdc axi4-lite

Verilog 42 11 GNU Lesser General Public License v2.1 Updated Jun 5, 2021
core_usb_cdc Public

Basic USB-CDC device core (Verilog)

fpga usb verilog usb-cdc usb-device

Verilog 86 20 GNU Lesser General Public License v2.1 Updated May 15, 2021
core_axi_cache Public

128KB AXI cache (32-bit in, 256-bit out)

Verilog 55 7 BSD 3-Clause "New" or "Revised" License Updated May 10, 2021
rp2040_blinky Public

Simple blinky example for the RP2040 that does not require cmake

C++ 5 BSD 3-Clause "New" or "Revised" License Updated Apr 26, 2021
riscv-linux-boot Public

Trivial RISC-V Linux binary bootloader

bootstrap linux-kernel bootloader uart risc-v atomics riscv-linux

C 54 11 MIT License Updated Apr 3, 2021
ps1-tests Public
Forked from JaCzekanski/ps1-tests

Collection of PlayStation 1 tests for emulator development

C++ 2 1 MIT License Updated Feb 7, 2021
core_mpx Public

MPX is a open-source CPU which can execute code compiled for MIPS-I ISA

Verilog 12 1 Apache License 2.0 Updated Nov 21, 2020
FPGAmp Public

720p FPGA Media Player (RISC-V + Motion JPEG + SD + HDMI on an Artix 7)

fpga mjpeg hdmi sd-card motion-jpeg rtos vga

C 294 46 Apache License 2.0 Updated Nov 21, 2020
core_jpeg_decoder Public

HW JPEG decoder wrapper with AXI-4 DMA

Verilog 36 6 Apache License 2.0 Updated Oct 25, 2020
legacy_jpeg_decoder Public archive
Forked from nekomona/aq_axis_djpeg

Verilog 10 2 MIT License Updated Oct 25, 2020
.github Public

Updated Oct 25, 2020
librtos Public

Very basic real time operating system for embedded systems...

C 17 5 Apache License 2.0 Updated Sep 19, 2020
core_mmc Public

MMC (and derivative standards) host controller

Verilog 25 5 Apache License 2.0 Updated Sep 14, 2020
orangecrab Public

Test projects for the OrangeCrab ECP5 FPGA board

Verilog 8 3 Apache License 2.0 Updated Aug 21, 2020
ecpix5-test Public

Test code / bitstreams for the LambdaConcept ECPIX-5 FPGA board

Verilog 8 Apache License 2.0 Updated Aug 20, 2020

ultraembedded

Sponsors

Achievements

Achievements

libhelix-mp3 Public

Uh oh!

libsigrok Public

Uh oh!

core_jpeg Public

Uh oh!

core_enet Public

Uh oh!

core_spiflash Public

Uh oh!

core_ddr3_controller Public

Uh oh!

riscv Public

Uh oh!

biriscv Public

Uh oh!

exactstep Public

Uh oh!

core_uriscv Public

Uh oh!

openFPGALoader Public

Uh oh!

cores Public

Uh oh!

core_dbg_bridge Public

Uh oh!

openlogicbit Public

Uh oh!

core_ftdi_bridge Public

Uh oh!

core_usb_bridge Public

Uh oh!

core_usb_cdc Public

Uh oh!

core_axi_cache Public

Uh oh!

rp2040_blinky Public

Uh oh!

riscv-linux-boot Public

Uh oh!

ps1-tests Public

Uh oh!

core_mpx Public

Uh oh!

FPGAmp Public

Uh oh!

core_jpeg_decoder Public

Uh oh!

legacy_jpeg_decoder Public archive

Uh oh!

.github Public

Uh oh!

librtos Public

Uh oh!

core_mmc Public

Uh oh!

orangecrab Public

Uh oh!

ecpix5-test Public

Uh oh!