Open-source high-performance RISC-V processor

Chisel: A Modern Hardware Design Language

Rocket Chip Generator

SonicBOOM: The Berkeley Out-of-Order Machine

Berkeley's Spatial Array Generator

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

A Chisel RTL generator for network-on-chip interconnects

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel

OpenSoC Fabric - A Network-On-Chip Generator

An open-source UCIe implementation

(System)Verilog to Chisel translator

A eDSL framework based on Scala and MLIR, focusing on the Hardware design.

chipyard in mill :P

A Heterogeneous GPU Platform for AI and Neural Graphics

A Scala library for Context-Dependent Environments

Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.

An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different manufacturers and models through parameter configuration.

Open-source RISC-V cryptographic hardware token, RTL repo

RTL blocks compatible with the Rocket Chip Generator

The working draft to split rocket core out from rocket chip

A PS/2 controller IP written in Chisel

A libre implementation of FPGA. Written by chisel.

chipyard in mill :P