Learn how to design large-scale systems. Prep for the system design interview. Includes Anki flashcards.

All Algorithms implemented in Python

List of awesome open source hardware tools, generators, and reusable designs

Package manager and build abstraction tool for FPGA/ASIC development

An abstraction library for interfacing EDA tools

RAG evaluation without the need for "golden answers"

Python bindings for slang, a library for compiling SystemVerilog

Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.

Pipeline parallelism for the minimalist

Automatic SystemVerilog linting in github actions with the help of Verible

Generate ctypes boilerplate code from debugging information; Use python to mock C code for testing

Generates a SystemVerilog assertion interface for a given SV RTL design

Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users can roll out their own linters!

Transaction based verification in Python

Code for Packt's Nexus Workshop on Building Agents using CrewAI

TB_LINT - Modular Linting Framework