Learn how to design large-scale systems. Prep for the system design interview. Includes Anki flashcards.

SystemVerilog file list pruner

Code for Packt's Nexus Workshop on Building Agents using CrewAI

Generative AI Integration Patterns,1E_Published by Packt

GPU Engineering for AI Systems

Transaction based verification in Python

TB_LINT - Modular Linting Framework

SVDB Gateway : DPI-C library that links SystemVerilog simulations with external SQLite databases for configuration, logging, and verification.

IceCream for SystemVerilog: Never use $display and `uvm_info to debug SystemVerilog again.

SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)

PSSGen: Portable Test and Stimulus Standard DSL Generator

SystemVerilog linter

Automatic SystemVerilog linting in github actions with the help of Verible

VS Code extension for SystemVerilog design navigation and RTL tracing. Seamlessly integrates with waveform viewer for post-simulation debug

Linter for SystemVerilog Assertions (SVA). Following the philosophy of BYOL - Build Your Own Linter, SVALint is an example of ho users can roll out their own linters!

This Repo consists the python note books of IITM - Mathematical Foundations for Generative AI Course,

Waveform Viewer Extension for VScode

Pipeline parallelism for the minimalist

SystemVerilog tutorial on how and why to use clocking blocks

21 Lessons, Get Started Building with Generative AI

Implement a ChatGPT-like LLM in PyTorch from scratch, step by step

Everything you need to know about LLM inference

mirror and fork of verilog code coverage tool from http://hg.code.sf.net/p/covered/code

lowRISC Style Guides

This python script uses pyslang module to parse design file and collects input,output and parameter information. Based on the data, the tb_creator script will generate UVM based testbench.

12 weeks, 26 lessons, 52 quizzes, classic Machine Learning for all

Courses, sample code, articles & screencasts - AWS, Azure, & GCP

A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.