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  • IC Verimeter
  • Ottawa, Ontario, Canada
  • 19:53 (UTC -05:00)

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verilog-meetup / non-uvm-axi-lite-verification-ip

Forked from yuri-panchul/non-uvm-axi-lite-verification-ip

Non-UVM AXI-Lite Verification IP. Started as an educational examples in older Valid-Ready-Etc repo for the Digital Circuit Synthesis School

SystemVerilog 8 Updated Aug 5, 2025

iic-jku / verilog-covered

Forked from Manarabdelaty/verilog-covered

mirror and fork of verilog code coverage tool from http://hg.code.sf.net/p/covered/code

C 5 1 Updated Apr 7, 2022