CS4192

Single Air-Core Gauge

Driver
The CS4192 is a monolithic BiCMOS integrated circuit used to
translate a digital 10–bit word from a microprocessor/microcontroller
to complementary DC outputs. The DC outputs drive an air–core
meter commonly used in vehicle instrument panels. The 10 bits of data http://onsemi.com
are used to linearly control the quadrature coils of the meter directly
with a 0.35° resolution and ±1.2° accuracy over the full 360° range of
the gauge. The interface from the microcontroller is by a Serial 16
Peripheral Interface (SPI) compatible serial connection using up to a
2.0 MHz shift clock rate. 1
The digital code, which is directly proportional to the desired gauge SO–16L
pointer deflection, is shifted into a DAC and multiplexer. These two DWF SUFFIX
blocks provide a tangential conversion function to change the digital CASE 751G
data into the appropriate DC coil voltage for the angle demanded. The
tangential algorithm creates approximately 40% more torque in the PIN CONNECTION AND
meter movement than does a sin–cos algorithm at 45°, 135°, 225°, and MARKING DIAGRAM
315° angles. This increased torque reduces the error due to pointer 1 16
droop at these critical angles. SIN– COS+
SIN+ COS–
Each output buffer is capable of supplying up to 70 mA per coil and

AWLYYWW
VBB SO
the buffers are controlled by a common OE enable pin. The output

CS4192
GND GND
buffers are turned off when OE is brought low, while the logic portion GND GND
of the chip remains powered and continues to operate normally. OE SI ST
must be high before the falling edge of CS to enable the output buffers. VCC CS
The status pin (ST) reflects the state of the outputs and is low OE SCLK
whenever the outputs are disabled.
The Serial Gauge Driver is self–protected against fault conditions. A = Assembly Location
Each driver is protected for 125 mA (typ.) overcurrent while a global WL, L = Wafer Lot
thermal protection circuit limits junction temperature to 170°C (typ.). YY, Y = Year
WW, W = Work Week
The output drivers are disabled anytime the IC protection circuitry
detects an overcurrent or overtemperature fault. The drivers remain
disabled until a falling edge is presented on CS. If the fault is still
present, the output drivers automatically disable themselves again. ORDERING INFORMATION
Device Package Shipping
Features
• Serial Input Bus
CS4192XDWF16 SO–16L 46 Units/Rail

• 2.0 MHz Operating Frequency CS4192XDWFR16 SO–16L 1000 Tape & Reel

• Tangential Drive Algorithm

• 70 mA Drive Circuits
• 0.5° Accuracy (Typ.)
• Power–On–Reset
• Protection Features
– Output Short Circuit
– Overtemperature
• Internally Fused Leads in SO–16L Package

 Semiconductor Components Industries, LLC, 2001 1 Publication Order Number:

December, 2001 – Rev. 6 CS4192/D
 CS4192

VCC VBB

POR LOGIC

ÇÇÇÇÇ
ÇÇÇÇÇ
SI Serial VTOP ÇÇÇÇÇ
ÇÇÇÇÇ
SIN+

ÇÇÇÇÇ
to
SCLK SIN–
Parallel D0–D6 7 Bit VVAR

ÇÇÇÇÇ
MUX
CS Shift DAC

ÇÇÇÇÇ
Register VBAT
COS+

ÇÇÇÇÇ
SO

ÇÇÇÇÇ
D7–D9 COS–

ÇÇÇÇÇ
POR
Overcurrent

ÇÇÇÇÇ
R FAULT Output
Latch S

ÇÇÇÇÇ
Amplifiers
ST Q
ENA

OE Overtemp

GND

Figure 1. Block Diagram

MAXIMUM RATINGS*
Rating Value Unit

Supply Voltage VBB –1.0 to 16.5

V
VCC –1.0 to 6.0

Digital Inputs –1.0 to 6.0 V

Steady State Output Current ±100 mA

Forced Injection Current (Inputs and Supply) ±10 mA

Operating Junction Temperature, (TJ) 150 °C

Storage Temperature Range –65 to 150 °C

Lead Temperature Soldering Reflow (SMD styles only) Note 1 230 peak °C

ESD Susceptibility (Human Body Model) 2.0 kV

Package Thermal Resistance, SO–16L

Junction–to–Case, RθJC 18 °C/W
Junction–to–Ambient, RθJA 75 °C/W

1. 60 seconds max above 183°.

*The maximum package power dissipation must be observed.

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 CS4192

ELECTRICAL CHARACTERISTICS (–40°C ≤ TJ ≤ 105°C; 7.5 V ≤ VBB ≤ 14 V, 4.5 V ≤ VCC ≤ 5.5 V;

unless otherwise specified. Note 2.)

Characteristic Test Conditions Min Typ Max Unit

Supply Voltages and Currents

VBB Quiescent Current Output disabled (OE = 0 V) – 1.0 5.0 mA
[RCOS, RSIN = RL(MIN)] @ 45° – – 175 mA
(code = X’080) VBB = 14 V

VCC Quiescent Current OE, CS, DI = high, VBB = 0 V, SCLK = 2.0 MHz – – 1.15 mA

Digital Inputs and Outputs

Output High Voltage SO, IOH = 0.8 mA VCC – 0.8 – – V

Output Low Voltage SO, IOL = 0.8 mA – – 0.4 V

ST, IOL = 2.5 mA – – 0.8 V

Output Off Leakage ST, VCC = 5.0 V – – 25 µA

Input High Voltage CS, SCLK, SI, OE 0.7 × VCC – – V

Input Low Voltage CS, SCLK, SI, OE – – 0.3 × V

VCC

Input High Current CS, SCLK, SI, OE; VIN = 0.7 × VCC – – 1.0 µA

Input Low Current CS, SCLK, SI, OE; VIN = 0.3 × VCC – – 1.0 µA

Analog Outputs
Output Function Accuracy – –1.2 ±0.5 +1.2 deg

Output Shutdown Current, Source VBB = 14 V 70 125 250 mA

Output Shutdown Current, Sink VBB = 14 V 70 125 250 mΑ

Output Shutdown Current, Source VBB = 7.5 V 43 125 250 mΑ

Output Shutdown Current, Sink VBB = 7.5 V 43 125 250 mΑ

Thermal Shutdown – – 170 – °C

Thermal Shutdown Hysteresis – – 20 – °C

Coil Drive Output Voltage – – 0.748 × VBB – V

Minimum Load Resistance TA = 105°C – 229 – Ω

TA = 25°C – 171 – Ω
TA = –40°C – 150 – Ω

Shift Clock Frequency – – – 2.0 MHz

SCLK High Time – 175 – – ns

SCLK Low Time – 175 – – ns

SO Rise Time 0.75 V to VCC – 1.2 V; CL = 90 pF – – 150 ns

SO Fall Time 0.75 V to VCC – 1.2 V; CL = 90 pF – – 150 ns

SO Delay Time CL = 90 pF – – 150 ns

SI Setup Time – 75 – – ns

SI Hold Time – 75 – – ns

CS Setup Time Note 3. 0 – – ns

CS Hold Time – 75 – – ns

2. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested
in production.
3. OE must be high at falling edge of CS. This condition ensures valid output for any given input.

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 CS4192

PIN FUNCTION DESCRIPTION

PACKAGE PIN # PIN SYMBOL FUNCTION
16 Lead SO Wide

1 SIN– Negative output for SINE coil.

2 SIN+ Positive output SINE coil.

3 VBB Analog supply. Nominally 13.5 V.

4, 5, 12, 13 GND Ground.

6 SI Serial data input. Data present at the rising edge of the clock
signal is shifted into the internal shift register.

7 VCC 5.0 V logic supply. The internal registers and latches are
reset by a POR generated by the rising edge of the voltage
on this pin.

8 OE Controls the state of the output buffers. A logic low on this

pin turns them off.

9 SCLK Serial clock for shifting in/out of data. Rising edge shifts data
on SI into the shift register and the falling edge changes the
data on SO.

10 CS When high allows data at SI to be shifted into part with the

rising edges of SCLK. The falling edge transfers the shift
register contents into the DAC and multiplexer to update the
output buffers. The falling edge also reenables the output
drivers if they have been disabled by a fault.

11 ST STATUS reflects the state of the outputs and is low anytime

the outputs are disabled, either by OE or the internal protec-
tion circuitry. Requires external pull–up resistor.

14 SO Serial data output. Existing 10–bit data is shifted out when

new data is shifted in. Allows cascading of multiple devices
on common serial port.

15 COS– Negative output for COSINE coil.

16 COS+ Positive output for COSINE coil.

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 CS4192

APPLICATIONS INFORMATION

THEORY OF OPERATION Quadrant II

The SACD is for interfacing between a microcontroller or
microprocessor and air–core meter movements commonly
 180°–Tan–1 VVCOS
SIN  VSIN 
 VCOS
used in automotive vehicles for speedometers and
tachometers. These movements are built using two coils For
 90.176°to 134.824° :
placed at a 90° orientation to each other. A magnetized disc
VSIN  0.748
VBB
floats in the middle of the coils and responds to the magnetic
field generated by each coil. The disc has a shaft attached to VCOS  Tan (
 90°)
0.748
VBB
it that protrudes out of the assembly. A pointer indicator is
attached to this shaft and in conjunction with a separate For
 135.176°to 179.824° :
printed scale displays the vehicle’s speed or the engine’s
VSIN  Tan(180° 
)
0.748
VBB
speed.
The disc (and pointer) respond to the vector sum of the VCOS  0.748
VBB
voltages applied to the coils. Ideally, this relationship
Quadrant III
follows a sine/cosine equation. Since this is a transcendental
and non–linear function, devices of this type use an
 180°  Tan–1 VVCOS
SIN  VSIN 
 VCOS
approximation for this relationship. The SACD uses a
tangential algorithm as shown in Figure 2. Only one output
varies in any 45 degree range. For
 180.176°to 224.824° :
VSIN  Tan (
 180°)
0.748
VBB
Degrees of Rotation
VCOS  0.748
VBB
0° 45° 90° 135° 180° 225° 270° 315° 360°
Max(128)

SIN+
For
 225.176°to 269.824° :
Output Min(0) VSIN  0.748
VBB
Max(128) VCOS  Tan (270° 
)
0.748
VBB
SIN–
Output Min(0) Quadrant IV

Max(128)
 360°  Tan–1 

VSIN  VSIN
VCOS  VCOS

COS+
Output
Min(0)
For
 270.176°to 314.824° :
Max(128) VSIN  0.748
VBB
COS– VCOS  Tan(
 270°)
0.748
VBB
Output Min(0)

000 001 010 011 100 101 110 111 000

For
 315.176°  359.824° :
MUX bits (D9–D7)
VSIN  Tan (360° 
)
0.748
VBB
Figure 2. SIN, COS Outputs
VCOS  0.748
VBB
Quadrant I

 Tan–1 
VSIN  VSIN
VCOS  VCOS


For
 0.176°to 44.824° :

VSIN  Tan

0.748
VBB
VCOS  0.748
VBB

For
 45.176°to 89.824° :

VSIN  0.748
VBB
VCOS  Tan(90° 
)
0.748
VBB

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 CS4192

VCOS+ The 10 bits are shifted into the device’s shift register MSB
360/0°
0.748 VBB
first using an SPI compatible scheme. This method is shown
in Figure 5. The CS must be high and remain high for SCLK
to be enabled. Data on SI is shifted in on the rising edge of
θ
the synchronous clock signal. Data in the shift register
IV
I
changes at SO on the falling edge of SCLK. This
arrangement allows the cascading of devices. SO is always
270° 90°
VSIN– 0.748 VBB 0.748 VBB VSIN+
enabled. Data shifts through without affecting the outputs
until CS is brought low. At this time the internal DAC is
III II
updated and the outputs change accordingly.

CS
0.748 VBB CSSetup CSHold
180°
VCOS– SCLK
SI(Setup) SI(Hold)
Figure 3. Gauge Response
SI
To drive the gauge’s pointer to a particular angle, the
microcontroller sends a 10–bit digital word into the serial SO
SO(Rise, Fall)
10% – 90%
port. These 10 bits are divided as shown in Figure 4. SI(tpd)

MSB LSB Figure 5. Serial Data Timing Diagram

Gauge D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(360°)
D9–D7 select Divides a 45° octant into 128 equal parts to Figure 6 shows the power–up sequence for the CS4192.
which octant achieve a 0.35° resolution Code 0–12710 Note the IC requires a pulse on the Chip Select (CS) pin to
Figure 4. Definition of Serial Word clear the Status Fault (ST) after power up. OE must be high
before the falling edge of CS to enable the output buffers.
However, from a software programmers viewpoint, a
360° circle is divided into 1024 equal parts of 0.35° each.
Table 1 shows the data associated with the 45° divisions of VCC
the 360° driver.
CS
Table1. Nominal Output (VBB = 14 V) 10 10
SI
Bits Bits
Input Code Ideal Nominal VSIN VCOS
(Decimal) Degrees Degrees (V) (V)
set to zero
Registers

0 0 0.176 0.032 10.476 OE

set to zero
Registers

128 45 45.176 10.476 10.412

ST
256 90 90.176 10.476 –0.032
OUTPUTS OUTPUTS
384 135 135.176 10.412 –10.476 ENABLED ENABLED

512 180 180.176 –0.032 –10.476

Figure 6. Power Up Sequence
640 225 225.176 –10.476 –10.412
768 270 270.176 –10.476 0.032
896 315 315.176 –10.476 10.476
1023 359.65 359.826 –0.032 10.476

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 CS4192

VREG 5.0 V
VBATT
CS8156 12 V

ENABLE

360° Gauge

CS4192

10 k SIN– COS+
SIN+ COS–
ST VBB
CS VCC
Microcontroller
SI
SCLK
SO Next Driver
OE

Figure 7. Application Diagram

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 CS4192

PACKAGE DIMENSIONS

SO–16L
DWF SUFFIX
CASE 751G–03
ISSUE B

D A


16 9 NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
M

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.
B

3. DIMENSIONS D AND E DO NOT INLCUDE MOLD

H

PROTRUSION.

h X 45

M

E
8X

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

0.25

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
1 8 CONDITION.

MILLIMETERS
16X B B DIM MIN MAX
A 2.35 2.65
0.25 M T A S B S A1 0.10 0.25
B 0.35 0.49
C 0.23 0.32
D 10.15 10.45
E 7.40 7.60
e 1.27 BSC
A

H 10.05 10.55
h 0.25 0.75
L

SEATING
PLANE L 0.50 0.90
14X e
0
7

A1

T C

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without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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