DRV8243-Q1

SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

DRV8243-Q1 Automotive H-Bridge Driver with Integrated Current Sense and

Diagnostics

1 Features 3 Description
• AEC-Q100 qualified for automotive applications: The DRV824x-Q1 family of devices is a fully
– Temperature grade 1: –40°C to +125°C, TA integrated H-bridge driver intended for a wide
• Functional Safety-Capable range of automotive applications. The device can
– Documentation available to aid functional safety be configured as a single full-bridge driver or as
system design two independent half-bridge drivers. Designed in a
• 4.5-V to 35-V (40-V abs. max) operating range BiCMOS high power process technology node, this
• VQFN-HR package: RON_LS + RON_HS: 84 mΩ monolithic family of devices in a power package
• HVSSOP package: RON_LS + RON_HS: 98 mΩ offer excellent power handling and thermal capability
• IOUT Max = 12 A while providing compact package size, ease of layout,
• PWM frequency operation up to 25 KHz with EMI control, accurate current sense, robustness, and
automatic dead time assertion diagnostic capability. This family also has identical
• Configurable slew rate and spread spectrum pin function with scalable RON (current capability) to
clocking for low electromagnetic interference (EMI) support different loads.
• Integrated current sense (eliminates shunt resistor) The devices integrate a N-channel H-bridge, charge
• Proportional load current output on IPROPI pin pump regulator, high-side current sensing and
• Configurable current regulation regulation, current proportional output, and protection
• Protection and diagnostic features with circuitry. A low-power sleep mode is provided to
configurable fault reaction (latched or retry) achieve low quiescent current. The devices offer
– Load diagnostics in both the off-state and on- voltage monitoring and load diagnostics as well
state to detect open load and short circuit as protection features against over current and
– Voltage monitoring on supply (VM) over temperature. Fault conditions are indicated on
– Over current protection nFAULT pin. The devices are available in three
– Over temperature protection variants - hardwired interface: HW (H) and two SPI
– Fault indication on nFAULT pin interface variants: SPI(P) and SPI(S), with SPI (P)
• Supports 3.3-V, 5-V logic inputs for externally supplied logic supply and SPI (S) for
• Low sleep current - 1μA typical at 25°C internally generated logic supply. The SPI interface
• 3 variants - HW (H), SPI (S) or SPI (P) variants offer more flexibility in device configuration
• Configurable control modes: and fault observability.
– Single full bridge using PWM or PH/EN mode
Device Information(1)
– Two half-bridges using Independent mode
PART NUMBER PACKAGE BODY SIZE (nominal)
• Device family comparison table
DRV8243-Q1 VQFN-HR (14) 3 mm X 4.5 mm
2 Applications DRV8243-Q1(2) HVSSOP (28) 3 mm X 7.3 mm
• Automotive brushed DC motors, Solenoids
(1) For all available packages, see the orderable addendum at
• Door modules , mirror modules, and seat modules the end of the data sheet
• Body control module (BCM) (2) Device available for preview only.
• E-Shifter
4.5 - 35 V
• Gas engine systems
• On board charger nSLEEP DRV824X-Q1
Driver Control
IOs

nFAULT
SPI (SPI variant) Full Bridge
Controller

Driver
CONFIG pins
(HW variant) Diagnoscs
IPROPI
Current Sense
ADC
Current Regula on
Built-in Protec
on

Simplified Schematic

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

Table of Contents
1 Features............................................................................1 8.3 Feature Description...................................................33
2 Applications..................................................................... 1 8.4 Device Functional States.......................................... 46
3 Description.......................................................................1 8.5 Programming - SPI Variant Only...............................49
4 Revision History.............................................................. 2 8.6 Register Map - SPI Variant Only............................... 53
5 Device Comparison......................................................... 3 9 Application and Implementation.................................. 60
6 Pin Configuration and Functions...................................6 9.1 Application Information............................................. 60
6.1 HW Variant..................................................................6 9.2 Typical Application.................................................... 61
6.2 SPI Variant.................................................................. 8 10 Power Supply Recommendations..............................65
7 Specifications................................................................ 11 10.1 Bulk Capacitance Sizing......................................... 65
7.1 Absolute Maximum Ratings...................................... 11 11 Layout........................................................................... 66
7.2 ESD Ratings..............................................................11 11.1 Layout Guidelines................................................... 66
7.3 Recommended Operating Conditions.......................12 11.2 Layout Example...................................................... 66
7.4 Thermal Information..................................................12 12 Device and Documentation Support..........................67
7.5 Electrical Characteristics...........................................12 12.1 Documentation Support.......................................... 67
7.6 SPI Timing Requirements......................................... 19 12.2 Receiving Notification of Documentation Updates..67
7.7 Switching Waveforms................................................21 12.3 Community Resources............................................67
7.8 Typical Characteristics.............................................. 27 12.4 Trademarks............................................................. 67
8 Detailed Description......................................................29 13 Mechanical, Packaging, and Orderable
8.1 Overview................................................................... 29 Information.................................................................... 67
8.2 Functional Block Diagram......................................... 30 13.1 Tape and Reel Information......................................71

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision * (November 2021) to Revision A (January 2022) Page

• Updated device status to Mixed Production....................................................................................................... 1

2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

5 Device Comparison
Table 5-1 summarizes the RON and package differences between devices in the DRV824X-Q1 family.
Table 5-1. Device Comparison
PART NUMBER(2) (LS + HS) RON IOUT MAX PACKAGE BODY SIZE (nominal) Variants
DRV8243-Q1 84 mΩ 12 A VQFN-HR (14) 3 mm X 4.5 mm HW (H), SPI (S)
DRV8243-Q1(3) 98 mΩ 12 A HVSSOP (28) 3 mm X 7.3 mm HW (H), SPI (S), SPI (P)
DRV8244-Q1 47 mΩ 21 A VQFN-HR (16) 3 mm X 6 mm HW (H), SPI (S)(1)
DRV8244-Q1 60 mΩ 21 A HVSSOP (28) 3 mm X 7.3 mm HW (H), SPI (S), SPI (P)
DRV8245-Q1 32 mΩ 32 A VQFN-HR (16) 3.5 mm X 5.5 mm HW (H)(1), SPI (S)
DRV8245-Q1 40 mΩ 32 A HTSSOP (28) 4.4 mm X 9.7 mm HW (H), SPI (S), SPI (P)

(1) DRV8245HRXZQ1 and DRV8244SRYJQ1 exceptions:

a. Off-state diagnostics (OLP) - This feature is NOT available for use in DRV8244SRYJQ1 (SPI(S) variant in VQFN-HR (16)
package) and DRV8245HRXZQ1 (HW(H) variant in VQFN-HR (16) package) - recommend to disable OLP in application.
b. Slew rate setting (SR = 3'b000, 3'b001, 3'b010) for DRV8244SRYJQ1 (SPI(S) variant in VQFN-HR (16) package) and LVL2 for
DRV8245HRXZQ1 (HW(H) variant in VQFN-HR (16) package) is NOT available in Independent mode operation using low-side
recirculation (low-side load) - recommend to use other settings for slew rate control.
(2) This is the product datasheet for the DRV8243-Q1. Please reference other device variant data sheets for additional information.
(3) Device available for preview only.

Table 5-2 summarizes the feature differences between the SPI and HW interface variants in the DRV824X-
Q1 family. In general, the SPI variant offers more configurability, bridge control options, diagnostic feedback,
redundant driver shutoff, improved Pin FMEA and additional features.
In addition, the SPI variant has two options - SPI (S) variant and SPI (P) variant. The SPI (P) variant supports
an external, low voltage 5 V supply to the device through the VDD pin for the device logic, whereas in the SPI
(S) variant, this supply is internally derived from the VM pin. With this external logic supply, the SPI (P) variant
avoids device brown out (reset of device) during VM under voltage transients.
Table 5-2. SPI Variant vs HW Variant Comparison
FUNCTION HW (H) Variant SPI (S) Variant SPI (P) Variant
Individual pin "and/or" register bit with pin status indication (Refer
Bridge control Pin only
Register Pin control)
Sleep function Available through nSLEEP pin Not available
External logic supply to the device Not supported Not supported Supported through VDD pin
Reset pulse on nSLEEP
Clear fault command SPI CLR_FAULT command
pin
Slew rate 6 levels 8 levels
Fixed at the highest
Over current protection (OCP) 3 choices for thresholds, 4 choices for filter time
setting
5 levels with disable &
ITRIP regulation 7 levels with disable & indication, with programmable TOFF time
fixed TOFF time
Individual fault reaction configuration Not supported, either all
Supported
between retry or latched behavior latched or all retry
Detailed fault logging and device status Not supported, nFAULT
Supported, nFAULT pin monitoring optional
feedback pin monitoring necessary
VM over voltage Fixed 4 threshold choices
On-state (Active) diagnostics Not supported Supported for high-side loads
Spread spectrum clocking (SSC) Not supported Supported
Additional driver states in PWM mode Not supported Supported
Hi-Z for individual half-bridge in
Not supported Supported (SPI register only)
Independent mode

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

Note
There are some functional improvements as well as parametric corrections between the pre-
production samples and final production devices. These differences are summarized in the feature
changes table and errata table. The sample types can be differentiated visually by their package
symbolization. Pre-production samples are pre-fixed with a "P" on the package symbolization.
Additionally, for the SPI variant, it is possible to electrically differentiate between the samples by
reading the DEVICE_ID register byte (refer to Table 5-5).

Table 5-3 summarizes the feature changes between the pre-production samples and final production devices.
Table 5-3. Feature Changes Between Pre-Production and Production Samples
Feature Pre-Production Samples Final Product
Parallel mode removed. Use the DRV814X equivalent
Parallel Mode Parallel mode available
device for this.
DRV824X: SR = ~[1.6 12* 18* 23 28 33 38 43] V/usec DRV824X: SR = ~[1.2 4* 6.7* 11.4 17 22 32 41] V/usec
Slew Rate HW only 6 choices only for high-side recirculation for high-side recirculation
*Additional settings in SPI variant only *Additional settings in SPI variant only
OCP limit in DRV8243 Set at 9 A min Increased to 12 A
VTRIP = [DIS 2.97 2.64 2.31 1.98 1.65* 1.41* 1.18] V
ITRIP regulation levels VTRIP = [DIS 2.97 2.64 2.31 1.98 1.65] V
*Additional settings in SPI only
DRVOFF_SEL, EN_IN1_SEL, PH_IN2_SEL
When SPI_IN is unlocked, the input pins, DRVOFF,
introduced to configure the logical combination
SPI variants only - Reg / EN_IN1 and PH_IN2, become don’t care and the
(AND/OR) of each of the three input pins (DRVOFF,
Pin control output is controlled by their equivalent register bits
EN/IN1, PH/IN2) with their register bit counterparts,
only.
when SPI_IN is unlocked. (Refer Register Pin control)
[IN1 IN2] = [H H] => HiZ, [L L] => Brake. This
PWM truth table [IN1 IN2] = [L L] => HiZ, [H H] => Brake eliminates risk for direction reversal for a short to GND
or Open in PWM mode.
Changes allow for efficient diagnostic monitoring, in
addition to support extended configurability
1. STATUS2 byte added for DRVOFF_STAT and
ACTIVE bit indication
SPI variants only - 2. OLP_CMP moved to STATUS2 with a redundant
As listed in the register map section
Register map expansion ACTIVE bit replacing OLP_CMP in the STATUS1
3. CONFIG4 byte added to accommodate
configurability for OCP control and output control
through input pins & their equivalent register bits

1. SPI variant - Feature enabled by default 1. SPI variant - Feature disabled by default
Spread spectrum clocking 2. HW variant - Feature always enabled 2. HW variant - Feature always disabled

Added 2 bits of OCP_SEL to lower OCP threshold and

Over current protection Fixed thresholds
2 bits of OCP_TSEL to change the OCP filter time.
Additional SPI (P) variant – nSLEEP/VIO pin function
SPI (P) variant Not available
changed to external VDD input as logic supply
Thresholds swapped in half-bridge operation to enable
Can't differentiate between open and short for a half-
OLP CMP reference differentiation between short and open for a half-bridge
bridge use case during off-state diagnostics (OLP)
use case during off-state diagnostics (OLP)
Processes write commands for Improved feature to process write commands for
1. length ≥ 16 SCLKs for regular SPI frame or 1. length = 16 SCLKs for regular SPI frame or
SPI variant only – Frame 2. length ≥ 16 + “N” x 16 SCLKs for daisy chain SPI 2. length = 16 + “N” x 16 SCLKs for daisy chain SPI
length error frame, where N = number of peripherals frame, where N = number of peripherals

Only shorter lengths are rejected with SPI_ERR All other lengths are rejected with SPI_ERR

4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

Table 5-4. Errata Fixes Between Pre-Production and Production Samples

Errata Pre-Production Samples Final Product
HW (H) variant only - Mean shift in Fixed the mean shift to ensure 10% resistor
Recommend to use 1% resistor on the
determining the resistance to GND at the (datasheet target) is OK for use on the
CONFIG pins to ensure expected behavior
CONFIG pins CONFIG pins as per datasheet
Digital input pin - hysteresis is lower than Hysteresis measured: [Min/ Typ/ Max] = [30/ Fixed to meet datasheet target of: [Min/ Typ/
expected 60/ 90] mV Max] = [70/ 100/ 150] mV
ITRIP regulation accuracy – lower than VTRIP threshold comparison could be ~ +/-
Fixed to meet datasheet target of < +/- 10%
expected 12%
Over current protection threshold mean shift
Fixed the mean value so that min OCP is
of high-side FET for DRV8245 closer to the OCP of HSx FET could be as low as 28 A
always > 32 A(datasheet target)
lower threshold

Table 5-5. Differentiating Between Pre-Production and Production Samples

Pre-Production Samples Final Product
Device
Package Symbolization DEVICE_ID Register Package Symbolization DEVICE_ID Register
DRV8243H-Q1 P8243X Not applicable 8243H Not applicable
DRV8244H-Q1 P8244X Not applicable 8244H Not applicable
DRV8245H-Q1 P8245X Not applicable 8245H Not applicable
DRV8243S-Q1 P8243X 0 x 30 8243S 0 x 32
DRV8244S-Q1 P8244X 0 x 40 8244S 0 x 42
DRV8245S-Q1 P8245X 0 x 50 8245S 0 x 52
DRV8243P-Q1 Not available 8243P 0 x 36
DRV8244P-Q1 Not available 8244P 0 x 46
DRV8245P-Q1 Not available 8245P 0 x 56

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

6 Pin Configuration and Functions

6.1 HW Variant

6.1.1 HVSSOP (28) package

SR 1 28 ITRIP

DIAG 2 27 MODE

PH/IN2 3 26 nFAULT

EN/IN1 4 25 IPROPI
DRVOFF 5 24 nSLEEP

Thermal Pad
VM 6 23 VM
VM 7 22 VM
VM 8 21 VM

OUT1 9 20 OUT2
OUT1 10 19 OUT2
OUT1 11 18 OUT2
GND 12 17 GND
GND 13 16 GND
GND 14 15 GND

Figure not drawn to scale

Figure 6-1. DRV8243H-Q1 HW variant in HVSSOP (28) package

Table 6-1. Pin Functions

PIN
TYPE(1) DESCRIPTION
NO. NAME
Device configuration pin for Slew Rate control . For details, refer to Slew Rate in the Device
1 SR I
Configuration section.
Device configuration pin for load type indication and fault reaction configuration. For details,
2 DIAG I
refer to DIAG in the Device Configuration section.
3 PH/IN2 I Controller input pin for bridge operation. For details, see the Bridge Control section.
4 EN/IN1 I Controller input pin for bridge operation. For details, see the Bridge Control section.
5 DRVOFF I Controller input pin for bridge Hi-Z. For details, see the Bridge Control section.
Power supply. This pin is the motor supply voltage. Must combine with the rest of VM pins
6, 7, 8, 21,
VM P (6 total) to support device current capability. Bypass this pin to GND with a 0.1-µF ceramic
22, 23
capacitor and a bulk capacitor.
Half-bridge output 1. Connect this pin to the motor or load. Must combine with the rest of
9, 10, 11 OUT1 P
OUT1 pins (3 total) to support device current capability.
12, 13, 14, Ground pin. Must combine with the rest of GND pins (6 total) to support device current
GND G
15, 16, 17 capability.
Half-bridge output 2. Connect this pin to the motor or load. Must combine with the rest of
18, 19, 20 OUT2 P
OUT2 pins (3 total) to support device current capability.
24 nSLEEP I Controller input pin for SLEEP. For details, see the Bridge Control section.
Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration
25 IPROPI I/O
section.
Fault indication to the controller. For details, refer to nFAULT in the Device Configuration
26 nFAULT OD
section.

6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

Table 6-1. Pin Functions (continued)

PIN
TYPE(1) DESCRIPTION
NO. NAME
27 MODE I Device configuration pin for MODE. For details, refer to the Device Configuration section.
Device configuration pin for ITRIP level for high-side current limiting. For details, refer to
28 ITRIP I
ITRIP in the Device Configuration section.

(1) I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output

6.1.2 VQFN-HR (14) package

14 MODE
MODE

DIAG
DIAG

13 ITRIP
ITRIP

12 SR
SR

11
14

13

12

11

nFAULT 1 10 PH/IN2 PH/IN2 10 1 nFAULT

IPROPI 2 9 EN/IN1 EN/IN1 9 2 IPROPI

nSLEEP 3 TOP VIEW 8 DRVOFF DRVOFF 8

BOTTOM VIEW 3 nSLEEP

VM 4 VM VM 4 VM

OUT2 5 7 OUT1 OUT1 7 5 OUT2

GND 6 GND GND 6 GND

GND GND GND GND GND GND GND GND

Figure not drawn to scale

Figure 6-2. DRV8243H-Q1 HW variant in VQFN-HR (14) package

Table 6-2. Pin Functions

PIN
TYPE (1) DESCRIPTION
NO. NAME
Fault indication to the controller. For details, refer to nFAULT in the Device Configuration
1 nFAULT OD
section.
Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration
2 IPROPI I/O
section.
3 nSLEEP I Controller input pin for SLEEP . For details, see the Bridge Control section.
Power supply. This pin is the motor supply voltage. Bypass this pin to GND with a 0.1-µF
4 VM P
ceramic capacitor and a bulk capacitor.
5 OUT2 P Half-bridge output 2. Connect this pin to the motor or load.
6 GND G Ground pin
7 OUT1 P Half-bridge output 1. Connect this pin to the motor or load.
8 DRVOFF I Controller input pin for bridge Hi-Z. For details, see the Bridge Control section.
9 EN/IN1 I Controller input pin for bridge operation. For details, see the Bridge Control section.
10 PH/IN2 I Controller input pin for bridge operation. For details, see the Bridge Control section.
Device configuration pin for load type indication and fault reaction configuration. For details,
11 DIAG I
refer to DIAG in the Device Configuration section.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

Table 6-2. Pin Functions (continued)

PIN
TYPE (1) DESCRIPTION
NO. NAME
Device configuration pin for Slew Rate control . For details, refer to Slew Rate in the Device
12 SR I
Configuration section.
Device configuration pin for ITRIP level for high-side current limiting. For details, refer to
13 ITRIP I
ITRIP in the Device Configuration section.
14 MODE I Device configuration pin for MODE. For details, refer to the Device Configuration section.

(1) I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output

6.2 SPI Variant

6.2.1 HVSSOP (28) package

SCLK 1 28 SDI SCLK 1 28 SDI

nSCS 2 27 SDO nSCS 2 27 SDO

PH/IN2 3 26 nFAULT PH/IN2 3 26 nFAULT

EN/IN1 4 25 IPROPI EN/IN1 4 25 IPROPI

DRVOFF 5 24 nSLEEP DRVOFF 5 24 VDD
Thermal Pad

Thermal Pad
VM 6 23 VM VM 6 23 VM
VM 7 22 VM VM 7 22 VM
VM 8 21 VM VM 8 21 VM

OUT1 9 20 OUT2 OUT1 9 20 OUT2

OUT1 10 19 OUT2 OUT1 10 19 OUT2
OUT1 11 18 OUT2 OUT1 11 18 OUT2
GND 12 17 GND GND 12 17 GND
GND 13 16 GND GND 13 16 GND
GND 14 15 GND GND 14 15 GND

Figure not drawn to scale Figure not drawn to scale

SPI (S) variant SPI (P) variant
Figure 6-3. DRV8243S-Q1 SPI variant in HVSSOP (28) package

Table 6-3. Pin Functions

PIN
TYPE (1) DESCRIPTION
NO. NAME
1 SCLK I SPI - Serial Clock input.
2 nSCS I SPI - Chip Select. An active low on this pin enables the serial interface communication.
3 PH/IN2 I Controller input pin for bridge operation. For details, see the Bridge Control section.
4 EN/IN1 I Controller input pin for bridge operation. For details, see the Bridge Control section.
5 DRVOFF I Controller input pin for bridge Hi-Z. For details, see the Bridge Control section.
Power supply. This pin is the motor supply voltage. Must combine with the rest of VM pins
6, 7, 8, 21,
VM P (6 total) to support device current capability. Bypass this pin to GND with a 0.1-µF ceramic
22, 23
capacitor and a bulk capacitor.
Half-bridge output 1. Connect this pin to the motor or load. Must combine with the rest of
9, 10, 11 OUT1 P
OUT1 pins (3 total) to support device current capability.

8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

Table 6-3. Pin Functions (continued)

PIN
TYPE (1) DESCRIPTION
NO. NAME
12, 13, 14, Ground pin. Must combine with the rest of GND pins (6 total) to support device current
GND G
15, 16, 17 capability.
Half-bridge output 2. Connect this pin to the motor or load. Must combine with the rest of
18, 19, 20 OUT2 P
OUT2 pins (3 total) to support device current capability.
SPI (S) variant: Controller input pin for SLEEP. For details, see the Bridge Control section.
nSLEEP I
24 Also VIO logic level for SDO.
VDD P SPI (P) variant: Logic power supply to the device.
Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration
25 IPROPI I/O
section.
Fault indication to the controller. For details, refer to nFAULT in the Device Configuration
26 nFAULT OD
section.
27 SDO PP SPI - Serial Data Output. Data is updated at the rising edge of SCLK.
28 SDI I SPI - Serial Data Input. Data is captured at the falling edge of SCLK.

(1) I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output

6.2.2 VQFN-HR (14) package

nSCS

SCLK
nSCS
SCLK

SDO
SDO

SDI
SDI

11

12

13

14
14

13

12

11

nFAULT 1 10 PH/IN2 PH/IN2 10 1 nFAULT

IPROPI 2 9 EN/IN1 EN/IN1 9 2 IPROPI

nSLEEP 3 TOP VIEW 8 DRVOFF DRVOFF 8

BOTTOM VIEW 3 nSLEEP

VM 4 VM VM 4 VM

OUT2 5 7 OUT1 OUT1 7 5 OUT2

GND 6 GND GND 6 GND

GND GND GND GND GND GND GND GND

Figure not drawn to scale

Figure 6-4. DRV8243S-Q1 SPI variant in VQFN-HR (14) package

Table 6-4. Pin Functions

PIN
TYPE (1) DESCRIPTION
NO. NAME
Fault indication to the controller. For details, refer to nFAULT in the Device Configuration
1 nFAULT OD
section.
Driver load current analog feedback. For details, refer to IPROPI in the Device Configuration
2 IPROPI O
section.
Controller input pin for SLEEP. For details, see the Bridge Control section. Also VIO logic
3 nSLEEP I
level for SDO.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

Table 6-4. Pin Functions (continued)

PIN
TYPE (1) DESCRIPTION
NO. NAME
Power supply. This pin is the motor supply voltage. Bypass this pin to GND with a 0.1-µF
4 VM P
ceramic capacitor and a bulk capacitor.
5 OUT2 P Half-bridge output 2. Connect this pin to the motor or load.
6 GND G Ground pin
7 OUT1 P Half-bridge output 1. Connect this pin to the motor or load.
8 DRVOFF I Controller input pin for bridge Hi-Z. For details, see the Bridge Control section.
9 EN/IN1 I Controller input pin for bridge operation. For details, see the Bridge Control section.
10 PH/IN2 I Controller input pin for bridge operation. For details, see the Bridge Control section.
11 nSCS I SPI - Chip Select. An active low on this pin enables the serial interface communication.
12 SCLK I SPI - Serial Clock input.
13 SDI I SPI - Serial Data Input. Data is captured at the falling edge of SCLK.
14 SDO PP SPI - Serial Data Output. Data is updated at the rising edge of SCLK.

(1) I = input, O = output, I/O = input/output, G = ground, P = power, OD = open-drain output, PP = push-pull output

10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

7 Specifications
7.1 Absolute Maximum Ratings
Over operating temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Power supply pin voltage VM –0.3 40 V
Power supply transient voltage ramp VM 2 V/µs
Output pin voltage OUT1, OUT2 -0.9 VVM + 0.9 V
Output pin current OUT1, OUT2 Internally limited(2) A
Driver disable pin voltage DRVOFF –0.3 40 V
Logic I/O voltage EN/IN1, PH/EN2, nFAULT –0.3 5.75 V
HW variant - Configuration pins voltage MODE, ITRIP, SR, DIAG –0.3 5.75 V
Analog feedback pin voltage IPROPI –0.3 5.75 V
Sleep pin voltage (Not applicable for SPI (P)
nSLEEP –0.3 40 V
variant)
SPI I/O voltage - SPI variant SDI, SDO, nSCS, SCLK –0.3 5.75 V
SPI (P) variant - Logic supply VDD -0.3 5.75 V
SPI (P) variant - Logic supply transient voltage
VDD 5 V/µs
ramp
Ambient temperature, TA –40 125 °C
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Limited by the over current and over temperature protection functions of the device

7.2 ESD Ratings

VALUE UNIT

Human body model (HBM), per AEC Q100-002(1) VM, OUT1, OUT2, GND ±4000
HBM ESD Classification Level 2 All other pins ±2000
Electrostatic
V(ESD) V
discharge
Charged device model (CDM), per AEC Q100-011 Corner pins ±750
CDM ESD Classification Level C4B Other pins ±500

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

7.3 Recommended Operating Conditions

over operating temperature range (unless otherwise noted)
MIN MAX UNIT
VVM Power supply voltage VM 4.5 35(1) V
VVDD SPI (P) variant - Logic supply voltage VDD 4.5 5.5 V
EN/IN1, PH/EN2, nSLEEP, DRVOFF,
VLOGIC Logic pin voltage 0 5.5 V
nFAULT
fPWM PWM frequency EN/IN1, PH/EN2 0 25 KHz
VCONFIG HW variant - Configuration pin voltage MODE, ITRIP, SR, DIAG 0 5.5 V
VIPROPI Analog feedback voltage IPROPI 0 5.5 V
VnSLEEP +
SPI (S) variant - SPI pin voltage SDI, SDO, nSCS, SCLK 0 V
VSPI_IOS 0.5
SPI (P) variant - SPI pin voltage SDI, SDO, nSCS, SCLK 0 VVDD + 0.5 V
TA Operating ambient temperature –40 125 °C
TJ Operating junction temperature –40 150 °C

(1) The over current protection function does not support direct output (OUT1, OUT2) shorts less than 1 μH above 28 V.

7.4 Thermal Information

Refer Transient thermal impedance table for application related use case.
THERMAL METRIC(1) HVSSOP package VQFN-HR package UNIT
RθJA Junction-to-ambient thermal resistance 31.0 48.4 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 29.1 22.3 °C/W
RθJB Junction-to-board thermal resistance 9.3 8.1 °C/W
ΨJT Junction-to-top characterization parameter 1.4 0.5 °C/W
ΨJB Junction-to-board characterization parameter 9.3 7.9 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance 1.3 N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

7.5 Electrical Characteristics

4.5 V (falling) ≤ VVM ≤ 35 V, -40°C ≤ TJ ≤ 150°C (unless otherwise noted)
For SPI (P) variant only: 4.5 V ≤ VVDD ≤ 5.5 V (unless otherwise noted)
7.5.1 Power Supply & Initialization
Refer wake up transient waveforms
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Supply pin voltage during reverse
VVM_REV IVM = - 5 A, device in unpowered state 1.4 V
current
VVM = 13.5 V, VnSLEEP = 0 V or VVDD <
1 µA
PORVDD_FALL, TA = 25°C
IVMQ VM current in SLEEP state
VVM = 13.5 V, VnSLEEP = 0 V or VVDD <
5.8 µA
PORVDD_FALL, TA = 125°C
IVMS VM current in STANDBY state VVM = 13.5 V 3 5 mA
IVDD VDD current in ACTIVE state SPI (P) variant 10 mA
Reset signal on nSLEEP pin for HW (H)
tRESET RESET pulse filter time 5 20 µs
variant
Sleep signal on nSLEEP pin for HW (H)
tSLEEP SLEEP command filter time 40 120 µs
variant

12 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Sleep signal on nSLEEP pin for SPI (S)
tSLEEP_SPI SLEEP command filter time 5 20 µs
variant
Wake-up signal on nSLEEP pin for HW
tWAKEUP Wake-up command filter time 10 µs
(H) and SPI (S) variants
Time for communication to be available Wake-up signal on nSLEEP pin or
tCOM after wake-up or power-up through VM power cycle - VVM > VMPOR_RISE or 400 µs
or VDD supply pin VVDD > VDDPOR_RISE
Time for driver ready to be driven after Wake-up signal on nSLEEP pin or
tREADY wake-up through nSLEEP pin or power- power cycle - VVM > VMPOR_RISE or 1 ms
up through VM or VDD supply pin VVDD > VDDPOR_RISE

7.5.2 Logic I/Os

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIL_nSLEEP Input logic low voltage nSLEEP pin 0.65 V
VIH_nSLEEP Input logic high voltage nSLEEP pin 1.55 V
VIHYS_nSLEE
Input hysteresis nSLEEP pin 200 mV
P

VIL Input logic low voltage DRVOFF, EN/IN1, PH/IN2 pins 0.7 V
VIH Input logic high voltage DRVOFF, EN/IN1, PH/IN2 pins 1.5 V
VIHYS Input hysteresis DRVOFF, EN/IN1, PH/IN2 pins 100 mV
Internal pull-down resistance on nSLEEP
RPD_nSLEEP Measured at min VIL level 100 400 KΩ
to GND
Internal pull-up resistance to VDD
RPU Measured at min VIH level 200 550 KΩ
(reverse current blocked) on DRVOFF
Internal pull-down resistance to GND on
RPD Measured at max VIL level 200 500 KΩ
EN/IN1 and PH/IN2
Sink current to GND on nFAULT pin
InFAULT_PD VnFAULT = 0.3 V 5 mA
when asserted low

7.5.3 SPI I/Os

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal pull-up resistance to VDD
RPU_nSCS Measured at min VIH level 200 500 KΩ
(reverse current blocked) on nSCS
Internal pull-down resistance to GND on
RPD_SPI Measured at max VIL level 150 500 KΩ
SDI, SCLK
VIL Input logic low voltage SDI, SCLK, nSCS pins 0.7 V
VIH Input logic high voltage SDI, SCLK, nSCS pins 1.5 V
VIHYS Input hysteresis SDI, SCLK, nSCS pins 100 mV
VOL_SDO Output logic low voltage 0.5 mA sink into SDO 0.4 V
0.5 mA source from SDO, VnSLEEP = 5
4.1 V
Output logic high voltage for SPI (S) V, VVM > 7 V
variant 0.5 mA source from SDO, VnSLEEP =
VOH_SDO 2.7 V
3.3 V, VVM > 5 V
Output logic high voltage for SPI (P)
0.5 mA source from SDO, VVDD = 5 V 4.5 V
variant
No current from SDO, VnSLEEP = 5 V,
5.5 V
Output logic high voltage at no load on VVM > 7 V
VOH_SDO_NL
SDO, valid only for SPI (S) variant No current from SDO, VnSLEEP = 3.3 V,
3.8 V
VVM > 5 V

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

7.5.4 Configuration Pins - HW Variant Only

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
6 level setting for ITRIP, SR and DIAG
RLVL1OF6 Level 1 of 6 Connect to GND 10 Ω
RLVL2OF6 Level 2 of 6 +/- 10% resistor to GND 7.4 8.2 9 KΩ
RLVL3OF6 Level 3 of 6 +/- 10% resistor to GND 19.8 22 24.2 KΩ
RLVL4OF6 Level 4 of 6 +/- 10% resistor to GND 42.3 47 51.7 KΩ
RLVL5OF6 Level 5 of 6 +/- 10% resistor to GND 90 100 110 KΩ
RLVL6OF6 Level 6 of 6 Hi-Z (no connect) 250 KΩ
3 level setting for MODE
RLVL1OF3 Level 1 of 3 Connect to GND 10 Ω
RLVL2OF3 Level 2 of 3 +/- 10% resistor to GND 7.4 8.2 9 KΩ
RLVL3OF3 Level 3 of 3 Hi-Z (no connect) 100 KΩ

7.5.5 Power FET Parameters

Measured at VVM = 13.5 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

High-side FET on resistance, HVSSOP IOUT = 3 A, TJ = 25°C 49 mΩ

package IOUT = 3 A, TJ = 150°C 93.1 mΩ
RHS_ON
High-side FET on resistance, VQFN-HR IOUT = 3 A, TJ = 25°C 42 mΩ
package IOUT = 3 A, TJ = 150°C 79.8 mΩ

Low-side FET on resistance, HVSSOP IOUT = 3 A, TJ = 25°C 49 mΩ

package IOUT = 3 A, TJ = 150°C 93.1 mΩ
RLS_ON
Low-side FET on resistance, VQFN-HR IOUT = 3 A, TJ = 25°C 42 mΩ
package IOUT = 3 A, TJ = 150°C 79.8 mΩ

Low-side & High-side FET source-drain

VSD voltage when body diode is forward IOUT = +/- 3 A (both directions) 0.4 0.9 1.5 V
biased

SR = 3'b000 or 3'b001 or 3'b010 or

2 5 KΩ
3'b111 or LVL2 or LVL5

SR = 3'b011 or LVL3 7 14 KΩ
OUT resistance to GND in SLEEP or
RHi-Z
STANDBY state, VOUTx = VVM = 13.5 V SR = 3'b100 or LVL4 5 10.5 KΩ

SR = 3'b101 or LVL1 4 8.5 KΩ

SR = 3'b110 or LVL6 2.5 6 KΩ

7.5.6 Switching Parameters with High-Side Recirculation

Load = 1.5mH / 4.7 Ohm, VVM = 13.5 V, refer high-side recirculation waveform

14 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SR = 3'b000 or LVL2 1.6 V/µs

SR = 3'b001 (SPI only) 5 V/µs

SR = 3'b010 (SPI only) 8 V/µs

SR = 3'b011 or LVL3 13.3 V/µs

SRLSOFF Output voltage rise time, 10% - 90%
SR = 3'b100 or LVL4 19 V/µs

SR = 3'b101 or LVL1 24.5 V/µs

SR = 3'b110 or LVL6 36 V/µs

SR = 3'b111 or LVL5 47 V/µs

SR = 3'b000 or LVL2 1 µs

SR = 3'b001 (SPI only) 0.9 µs

Propagation time during output voltage SR = 3'b010 (SPI only) 0.8 µs

tPD_LSOFF
rise SR = 3'b011 or LVL3 0.7 µs

SR = 3'b100 & 3'b101 or LVL4 & LVL1 0.6 µs

SR = 3'b110 & 3'b111 or LVL6 & LVL5 0.5 µs

tDEAD_LSOFF Dead time during output voltage rise All SRs 0.9 µs

SR = 3'b000 or LVL2 1.6 V/µs

SR = 3'b001 (SPI only) 5 V/µs

SR = 3'b010 (SPI only) 8 V/µs

SR = 3'b011 or LVL3 13.3 V/µs

SRLSON Output voltage fall time, 90% - 10%
SR = 3'b100 or LVL4 19 V/µs

SR = 3'b101 or LVL1 24.5 V/µs

SR = 3'b110 or LVL6 36 V/µs

SR = 3'b111 or LVL5 47 V/µs

SR = 3'b000 or LVL2 0.2 µs

SR = 3'b001 (SPI only) 0.2 µs

Propagation time during output voltage SR = 3'b010 (SPI only) 0.2 µs

tPD_LSON
fall SR = 3'b011 or LVL3 0.4 µs

SR = 3'b100 or 3'b101 or LVL4 or LVL1 0.3 µs

SR = 3'b110 & 3'b111 or LVL6 & LVL5 0.2 µs

SR = 3'b000 or LVL2 1.5 µs

SR = 3'b001 or 3'b010 (SPI only) 0.6 µs

tDEAD_LSON Dead time during output voltage fall
SR = 3'b011 or LVL3 0.7 µs

All other SRs 0.6 µs

Output voltage rise and fall slew rate

MatchSRLS All SRs -20 +20 %
matching

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 15

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

7.5.7 Switching Parameters with Low-Side Recirculation

Load = 1.5 mH / 4.7 Ohm, VVM = 13.5 V, refer low-side recirculation waveform
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SRHSON Output voltage rise time, 10% - 90% All SRs 8 V/µs
SR = 3'b000 or LVL2 3.1 µs
SR = 3'b001 (SPI only) 2 µs
Propagation time during output voltage
tPD_HSON SR = 3'b010 (SPI only) 1.7 µs
rise
SR = 3'b011 or LVL3 1.2 µs
All other SRs 0.9 µs
SR = 3'b000 or LVL2 1.5 µs
SR = 3'b001 (SPI only) 1 µs
tDEAD_HSON Dead time during output voltage rise
SR = 3'b010 (SPI only) 0.8 µs
All other SRs 0.45 µs
SR = 3'b000 or 3'b001 or 3'b010 or
43 V/µs
LVL2
SR = 3'b011 or LVL3 14 V/µs

SRHSOFF Output voltage fall time, 90% - 10% SR = 3'b100 or LVL4 19 V/µs
SR = 3'b101 or LVL1 24 V/µs
SR = 3'b110 or LVL6 34 V/µs
SR = 3'b111 or LVL5 43 V/µs
Propagation time during output voltage
tPD_HSOFF All SRs 0.25 µs
fall
tDEAD_HSOFF Dead time during output voltage fall All SRs 0.2 µs
Current regulation blanking time after
tBLANK OUT slewing for current sense output to All SRs 3.4 µs
settle (Valid for only for LS recirculation)

16 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

7.5.8 IPROPI & ITRIP Regulation

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current scaling factor, HVSSOP
3020 A/A
package
AIPROPI
Current scaling factor, VQFN-HR
3070 A/A
package
IOUT > 0.8 A to 4.3 A -5 +5 %
AI_ERR Current scaling factor error IOUT = 0.2 A to 0.8 A -20 +20 %
IOUT = 0.1 A to 0.2 A -50 +50 %
Current matching between the two half-
AI_ERR_M IOUT > 0.8 A -2 +2 %
bridges
Offset current on IPROPI at no load
OffsetIPROPI IOUT = 0 A 15 µA
current
Bandwidth of the IPROPI internal sense
BWIPROPI No external capacitor on IPROPI. 400 KHz
circuit
VIPROPI_LIM Internal clamping voltage on IPROPI 4.5 5.5 V
ITRIP = 3'b001 or LVL2 1.06 1.18 1.3 V
ITRIP = 3'b010 (SPI only) 1.27 1.41 1.55 V
ITRIP = 3'b011 (SPI only) 1.49 1.65 1.82 V
Voltage limit on VIPROPI to trigger TOFF
VITRIP_LVL ITRIP = 3'b100 or LVL3 1.78 1.98 2.18 V
cycle for ITRIP regulation
ITRIP = 3'b101 or LVL4 2.08 2.31 2.54 V
ITRIP = 3'b110 or LVL5 2.38 2.64 2.9 V
ITRIP = 3'b111 or LVL6 2.67 2.97 3.27 V
TOFF = 2'b00 (SPI only) 16 20 25 µs
TOFF = 2'b01 (SPI). Only choice for
24 30 36 µs
tOFF ITRIP regulation - off time HW
TOFF = 2'b10 (SPI only) 33 40 48 µs
TOFF = 2'b11 (SPI only) 41 50 61 µs

7.5.9 Over Current Protection (OCP)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OCP_SEL = 2'b00 (SPI), Only choice
12 24 A
for HW
Over current protection threshold on the
IOCP_HS
high side OCP_SEL = 2'b10 (SPI only) 9 18 A
OCP_SEL = 2'b01 (SPI only) 6 14 A
OCP_SEL = 2'b00 (SPI), Only choice
12 24 A
for HW
Over current protection threshold on the
IOCP_LS
low side OCP_SEL = 2'b10 (SPI only) 9 18 A
OCP_SEL = 2'b01 (SPI only) 6 14 A
TOCP_SEL = 2'b00 (SPI), Only choice
Over current protection deglitch time 4.5 6 7.3 µs
for HW

tOCP Over current protection deglitch time TOCP_SEL = 2'b01 (SPI only) 2.2 3 4.1 µs
Over current protection deglitch time TOCP_SEL = 2'b10 (SPI only) 1.1 1.5 2.3 µs
Over current protection deglitch time TOCP_SEL = 2'b11 (SPI only) 0.15 0.2 0.4 µs

7.5.10 Over Temperature Protection (TSD)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TTSD Thermal shutdown temperature 155 170 185 °C
THYS Thermal shutdown hysteresis 30 °C
tTSD Thermal shutdown deglitch time 10 12 19 µs

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 17

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

7.5.11 Voltage Monitoring

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VMOV_SEL = 2'b00 (SPI), Only choice
33.6 37 V
in HW variant
VVMOV VM over voltage threshold while rising
VMOV_SEL = 2'b01 (SPI only) 28 31 V
VMOV_SEL = 2'b10 (SPI only) 18 21 V
VVMOV_HYS VM over voltage hysteresis 0.6 V
tVMOV VM over voltage deglitch time 10 12 19 µs
VVMUV VM under voltage threshold while falling 4.2 4.5 V
VVMUV_HYS VM under voltage hysteresis 200 mV
tVMUV VM under voltage deglitch time 10 12 19 µs
VM voltage at which device goes into
VMPOR_FALL Applicable for HW & SPI (S) variant 3.6 V
POR
VM voltage at which device comes out of
VMPOR_RISE Applicable for HW & SPI (S) variant 3.9 V
POR
VDDPOR_FAL VDD voltage at which device goes into
Applicable for SPI (P) variant 3.5 V
L POR
VDDPOR_RIS VDD voltage at which device comes out
Applicable for SPI (P) variant 3.8 V
E of POR

7.5.12 Load Monitoring

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Off-state diagnostics (OLP)
Resistance on OUT to GND that will be
RS_GND 1 KΩ
detected as short, All modes
Resistance on OUT to VM that will be
RS_VM 1 KΩ
detected as short , All modes
Resistance between OUTx that will be
ROPEN_FB 1.5 KΩ
detected as open, PH/EN or PWM mode
Resistance on OUT to GND that will be
ROPEN_LS Valid for low-side load 2 KΩ
detected as open , Independent mode
Resistance on OUT to VM that will be
ROPEN_HS Valid for high-side load, VVM = 13.5 V 10 KΩ
detected as open, Independent mode
VOLP_REFH OLP Comparator Reference High 2.65 V
VOLP_REFL OLP Comparator Reference Low 2 V
Internal pull-up resistance on OUT to
ROLP_PU VOUTx = VOLP_REFH + 0.1V 1 KΩ
VDD during OLP
Internal pull-down resistance on OUT to
ROLP_PD VOUTx = VOLP_REFL - 0.1V 1 KΩ
GND during OLP
SPI variant only - On-state diagnostics (OLA)
SR = 3'b000 or 3'b001 or 3'b010 or
2.5 5 mA
3'b111 or LVL2 or LVL5
Internal sink current on OUT to SR = 3'b011 or LVL3 0.8 2 mA
IPD_OLA GND during dead-time in high-side
SR = 3'b100 or LVL4 1.2 2.5 mA
recirculation
SR = 3'b101 or LVL1 1.5 3 mA
SR = 3'b110 or LVL6 2.2 4 mA
Comparator Reference with respect to
VOLA_REF 0.25 V
VM used for OLA

7.5.13 Fault Retry Setting

Refer to retry setting waveform

18 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tRETRY Automatic driver retry time Fault reaction set to RETRY 4.1 5 6.1 ms
Fault free operation time to auto-clear
tCLEAR Fault reaction set to RETRY 85 200 µs
from over current event
Fault free operation time to auto-clear
tCLEAR_TSD Fault reaction set to RETRY 4.2 6.7 ms
from over temperature event

7.5.14 Transient Thermal Impedance & Current Capability

Information based on thermal simulations
Table 7-1. Transient Thermal Impedance (RθJA) and Current Capability - full-bridge
Current [A](2)
PACKA RθJA [°C/W](1)
PART NUMBER without PWM(3) with PWM(4)
GE
0.1 sec 1 sec 10 sec DC 0.1 sec 1 sec 10 sec DC 10 sec DC
VQFN-
DRV8243-Q1 7.3 13 17.5 34.2 7.5 5.6 4.8 3.5 4.4 3.0
HR
DRV8243-Q1 HVSSOP 5.8 10.5 15.3 32.4 7.8 5.8 4.8 3.3 4.4 2.9

(1) Based on thermal simulations using 40 mm x 40 mm x 1.6 mm 4 layer PCB – 2 oz Cu on top and bottom layers, 1 oz Cu on internal
planes with 0.3 mm thermal via drill diameter, 0.025 mm Cu plating, 1 minimum mm via pitch.
(2) Estimated transient current capability at 85 °C ambient temperature for junction temperature rise up to 150°C
(3) Only conduction losses (I2R) considered
(4) Switching loss roughly estimated by the following equation:
PSW = VVM x ILoad x fPWM x VVM/SR, where VVM = 13.5 V, fPWM = 20 KHz, SR = 23 V/µs (1)

7.6 SPI Timing Requirements

MIN NOM MAX UNIT
tSCLK SCLK minimum period(1) 100 ns
tSCLKH SCLK minimum high time 50 ns
tSCLKL SCLK minimum low time 50 ns
tHI_nSCS SDO minimum high time 300 ns
tSU_nSCS nSCS input setup time 25 ns
tH_nSCS nSCS input hold time 25 ns
tSU_SDI SDI input data setup time 25 ns
tH_SDI SDI input data hold time 25 ns
tEN_SDO SDO enable delay time(1) 35 ns
tDIS_SDO SDO disable delay time(1) 100 ns

(1) SPI (S) variant: SDO delay times are valid only with SDO external load of 5 pF. With a 20 pF load on SDO, there is an additional
delay on SDO, which results in a 25% increase in SCLK minimum time, limiting the SCLK to a maximum of 8 MHz. There is NO such
limitation for the SPI (P) variant.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 19

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

tHI_nSCS tSU_nSCS tH_nSCS

nSCS
tSCLK

SCLK
tSCLKH tSCLKL

SDI DON’T
X CARE MSB LSB X DON’T CARE

tSU_SDI tH_SDI
tDIS_SDO

SDO HI-Z
Z MSB LSB Z HI-Z

tEN_SDO
Write Command
executed by device
SDI capture point

SDO propogate point

Figure 7-1. SPI Peripheral-Mode Timing Definition

20 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

7.7 Switching Waveforms

This section illustrates the switching transients for an inductive load due to external PWM or internal ITRIP
regulation.
7.7.1.1 High-Side Recirculation

LOAD LOAD LOAD LOAD LOAD

1, 2 3 4, 5, 6 7 8, 1

1 2 3 4 5 6 7 8 1
Isense OK
tDEAD_LSOFF tDEAD_LSON
VM + VD(FET BODY DIODE)
VM
OUT1
90% ~SRHSON tPD_LSON ~SRHSOFF 90%
Accuracy not Accuracy not
applicable applicable

High side recircula
on SRLSON

SRLSOFF Slew rate controlled by Low Side Driver (SRLSON & SRLSOFF)
10% 10%

OUT2 GND
tPD_LSOFF

“fPWM” @ duty cycle “D”

EN/IN1

PH/IN2

E.g. Full bridge in PH/EN mode, OUT1 is held high, while OUT2 is switching

Figure 7-2. Output Switching Transients for a H-Bridge with High-Side Recirculation

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 21

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

LOAD LOAD LOAD LOAD LOAD

1, 2 3 4, 5, 6 7 8, 1

1 2 3 4 5 6 7 8 1

Isense NOT OK
tDEAD_LSOFF tDEAD_LSON
VM + VD(FET BODY DIODE)
VM
90% ~SRHSON tPD_LSON ~SRHSOFF 90%
Accuracy not Accuracy not
applicable applicable

High side recircula
on

SRLSOFF
Slew rate controlled by Low Side Driver (SRLSON & SRLSOFF) SRLSON

10% 10%

OUT1 GND
tPD_LSOFF
“fPWM” @ duty cycle “1-D”

IN1

E.g. High side load in Independent mode, OUT1 is switching

Figure 7-3. Output Switching Transients for a Half-Bridge with High-Side Recirculation

7.7.1.2 Low-Side Recirculation

LOAD LOAD LOAD LOAD LOAD

1, 2 3 4, 5, 6 7 8, 1

1 2 3 4 5 6 7 8 1

Isense OK Isense NOT OK Isense OK

OUT1 VM
90% 90% tBLANK
tPD_HSOFF

Low side recircula
on

SRHSOFF SRHSON
Slew rate controlled by High Side Driver (SRHSON & SRHSOFF)
10% 10%
~SRLSON ~SRLSOFF
Accuracy not applicable Accuracy not applicable

GND
GND - VD(FET BODY DIODE)
tDEAD_HSOFF tDEAD_HSON
tPD_HSON

“fPWM” @ duty cycle “D”

IN1

E.g. Low side load in Independent mode, OUT1 is switching

Figure 7-4. Output Switching Transients for a half-bridge with Low-Side Recirculation
22 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

7.7.2 Wake-up Transients

7.7.2.1 HW Variant

tWAKEUP tRESET

tREADY
nSLEEP
tCOM
nFAULT
nSLEEP RESET
pulse ACK
t2
t1
t0

t3

t5
t4
Figure 7-5. Wake-up from SLEEP State to STANDBY State Transition for HW Variant

Hand shake between controller and device during wake-up as follows:

• t0: Controller - nSLEEP asserted high to initiate device wake-up
• t1: Device internal state - Wake-up command registered by device (end of Sleep state)
• t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
• t3: Device internal state - Initialization complete
• t4 (any time after t2): Controller – Issue nSLEEP reset pulse to acknowledge device wake-up
• t5: Device - nFAULT de-asserted as an acknowledgement of nSLEEP reset pulse. Device in STANDBY state

tREADY

VM
VVMUV_HYST
VVMUV
VMPOR_RISE
VMPOR_FALL
Internal
nPOR tRESET

nSLEEP=
1'b1
tCOM
nFAULT
nSLEEP RESET
pulse ACK
t1
t0

t2

t4
t5
t3

Figure 7-6. Power-up to STANDBY State Transition for HW Variant

Hand shake between controller and device during power-up as follows:

• t0: Device internal state - POR asserted based on under voltage of internal LDO (VM dependent)
• t1: Device internal state – POR de-asserted based on recovery of internal LDO voltage
• t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
• t3: Device internal state - Initialization complete
• t4 (any time after t2): Controller – Issue nSLEEP reset pulse to acknowledge device power-up
• t5: Device - nFAULT de-asserted as an acknowledgement of nSLEEP reset pulse. Device in STANDBY state

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 23

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

7.7.2.2 SPI Variant

CLR_FLT
tWAKEUP cmd
tREADY
nSLEEP
tCOM
nFAULT
CLR_FLT
cmd ACK

t4
t2
t1
t0

t3

t5
Figure 7-7. Wake-up from SLEEP State to STANDBY State Transition for SPI (S) Variant

Hand shake between controller and device during a wake-up transient as follows:
• t0: Controller - nSLEEP asserted high to initiate device wake-up
• t1: Device internal state - Wake-up command registered by device (end of Sleep state)
• t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
• t3: Device internal state - Initialization complete
• t4 (Any time after t2): Controller – Issue CLR_FLT command through SPI to acknowledge device wake-up
• t5: Device - nFAULT de-asserted as an acknowledgement of nSLEEP reset pulse. Device in STANDBY state

tREADY

VM
CLR_FLT
VVMUV_HYST cmd
VVMUV
VMPOR_RISE
VMPOR_FALL
Internal
nPOR

nSLEEP=
1'b1 tCOM
nFAULT
CLR_FLT
cmd ACK
t1
t0

t2

t3

t5
t4

Figure 7-8. Power-up to STANDBY State Transition for SPI (S) Variant

Hand shake between controller and device during power-up as follows:

• t0: Device internal state - POR asserted based on under voltage of internal LDO (VM dependent)
• t1: Device internal state – POR de-asserted based on recovery of internal LDO voltage
• t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
• t3: Device internal state - Initialization complete
• t4 (Any time after t2): Controller – Issue CLR_FLT command through SPI to acknowledge device power-up
• t5: Device - nFAULT de-asserted as an acknowledgement of nSLEEP reset pulse. Device in STANDBY state

24 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

tREADY

VDD CLR_FLT
cmd
VDDPOR_RISE
VDDPOR_FALL
Internal
nPOR
tCOM
nFAULT
CLR_FLT
cmd ACK
t1
t0

t2

t4
t3

t5
Figure 7-9. Power-up to STANDBY State Transition for SPI (P) Variant

Hand shake between controller and device during power-up as follows:

• t0: Device internal state - POR asserted based on under voltage on VDD (external supply)
• t1: Device internal state – POR de-asserted based on recovery of voltage on VDD (external supply)
• t2: Device – nFAULT asserted low to acknowledge wake-up and indicate device ready for communication
• t3: Device internal state - Initialization complete
• t4 (Any time after t2): Controller – Issue CLR_FLT command through SPI to acknowledge device power-up
• t5: Device - nFAULT de-asserted as an acknowledgement of nSLEEP reset pulse. Device in STANDBY state

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 25

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

7.7.3 Fault Reaction Transients

7.7.3.1 Retry setting

Valid for both SPI and HW variants

tCLEAR
nFAULT

tOCP tOCP tOCP

IOCP tRETRY
tRETRY
I(VM) ILOAD
IVMQ

t4
t3

t6
t5
t1
t2

External short to ground fault

Figure 7-10. Fault reaction with RETRY setting (shown for OCP occurrence on high-side when OUT is
shorted to ground)

Short occurrence and recovery scenario with RETRY setting:

• t1: An external short occurs.
• t2: OCP (Over Current Protection) fault confirmed after tOCP, output disabled, nFAULT asserted low to
indicate fault.
• t3: Device automatically attempts retry (auto retry) after tRETRY. Each time output is briefly turned on to
confirm short occurrence and then immediately disabled after tOCP. nFAULT remains asserted low through
out. Cycle repeats till driver is disabled by the user or external short is removed, as illustrated further. Note
that, in case of a TSD (Thermal Shut Down) event, automatic retry time depends on the cool off based on
thermal hysteresis.
• t4: The external short is removed.
• t5: Device attempts auto retry. But this time, no fault occurs and device continues to keep the output enabled.
• t6: After a fault free operation for a period of tCLEAR is confirmed, nFAULT is de-asserted.
• SPI variant only – Fault status remains latched till a CLR_FLT command is issued.
Note that, in the event of an output short to ground causing the high-side OCP fault detection, IPROPI pin will
continue to be pulled up to VIPROPI_LIM voltage to indicate this type of short, while the output is disabled. This
is especially useful for the HW (H) variant to differentiate the indication of a short to ground fault from the other
faults.

26 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

7.7.3.2 Latch setting

Valid for both SPI and HW variants
CLR_FLT CMD (SPI) /
nSLEEP RESET PULSE (HW)
nFAULT

tOCP tOCP

IOCP
I(VM) ILOAD
IVMQ

t4
t3

t6
t5
t1
t2

External short to ground fault

Figure 7-11. Fault reaction with Latch setting (shown for OCP occurrence on high-side when OUT is
shorted to ground)

Short occurrence and recovery scenario with LATCH setting:

• t1: An external short occurs.
• t2: OCP (Over Current Protection) fault confirmed after tOCP, output disabled, nFAULT asserted low to
indicate fault.
• t3: A CLR_FLT command (SPI variant) or nSLEEP RESET Pulse (HW variant) issued by controller. nFAULT
is de-asserted and output is enabled. OCP fault is detected again and output is disabled with nFAULT
asserted low.
• t4: The external short is removed.
• t5: A CLR_FLT command (SPI variant) or nSLEEP RESET Pulse (HW variant) issued by controller. nFAULT
is de-asserted and output is enabled. Normal operation resumes.
• SPI variant only – Fault status remains latched till a CLR_FLT command is issued.
Note that, in the event of an output short to ground causing the high-side OCP fault detection, IPROPI pin will
continue to be pulled up to VIPROPI_LIM voltage to indicate this type of short, while the output is disabled. This
is especially useful for the HW (H) variant to differentiate the indication of a short to ground fault from the other
faults.
7.8 Typical Characteristics

66 3250
LS1 0.1A
63 3200 0.2A
LS2
60 HS1 3150 0.8A
HS2 4.3A
57 3100
FET RON [m]

54
AIPROPI [A/A]

3050
51 3000
48
2950
45
2900
42
2850
39
2800
36
2750
33 -40 -20 0 20 40 60 80 100 120 140 160
-40 -20 0 20 40 60 80 100 120 140 160 Temperature [C]
Temperature [C]
Figure 7-13. AIPROPI Gain vs Temperature at VVM =
Figure 7-12. RHS_ON & RLS_ON for VQFN-HR(16) vs
13.5 V
Temperature at VVM = 13.5 V

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 27

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

20.5

19.5

18.5
LS OCP Threshold [A]

17.5 OCP_SEL = 0
OCP_SEL = 2
16.5 OCP_SEL = 1
15.5

14.5

13.5

12.5

11.5
-40 -20 0 20 40 60 80 100 120 140 160
Temperature [C]

Figure 7-14. LS OCP Threshold vs Temperature at Figure 7-15. HS OCP Threshold vs Temperature at
VVM = 13.5 V VVM = 13.5 V
4
3.75
3.5
3.25
Standby current [mA]

3
VM 5V
2.75 VM 13.5V
VM 25V
2.5 VM 35V
2.25
2
1.75
1.5
1.25
-40 -20 0 20 40 60 80 100 120 140 160
Temperature [C]

Figure 7-16. Current on VM in STANDBY state vs Figure 7-17. Current on VM in SLEEP state vs
Temperature Temperature
100 100
SR = 3'b000 SR = 3'b000
90 SR = 3'b001 90 SR = 3'b001
SR = 3'b010 SR = 3'b010
Measured OUT duty cycle [%]

Measured OUT duty cycle [%]

80 80
SR = 3'b011 SR = 3'b011
70 SR = 3'b100 70 SR = 3'b100
SR = 3'b101 SR = 3'b101
60 SR = 3'b110 60 SR = 3'b110
50 SR = 3'b111 50 SR = 3'b111

40 40
30 30
20 20
10 10
0 0
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100
Input Duty Cycle [%] on EN/IN1 pin at 5 KHz PWM Input Duty Cycle [%] on EN/IN1 pin at 20 KHz PWM

Figure 7-18. Measured Duty Cycle vs Input Duty Figure 7-19. Measured Duty Cycle vs Input Duty
Cycle at PWM frequency of 5 KHz at VVM = 13.5 V Cycle at PWM frequency of 20 KHz at VVM = 13.5 V
for HS recirculation for HS recirculation

28 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

8 Detailed Description
8.1 Overview
The DRV824x-Q1 family of devices are brushed DC motor drivers that operate from 4.5 to 35-V supporting a
wide range of output load currents for various types of motors and loads. The devices integrate an H-bridge
output power stage that can be operated in different control modes set by the MODE function. This allows for
driving a single bidirectional brushed DC motor or two unidirectional brushed DC motors. The devices integrate
a charge pump regulator to support efficient high-side N-channel MOSFETs with 100% duty cycle operation.
The devices operate from a single power supply input (VM) which can be directly connected to a battery or DC
voltage supply. The devices also provide a low power mode to minimize current draw during system inactivity.
The devices are available in two interface variants -
1. HW variant - Hardwired interface variant is available for easy device configuration. Due to the limited number
of available pins in the device, this variant offers fewer configuration and fault reporting capability compared
to the SPI variant.
2. SPI variant - A standard 4-wire serial peripheral interface (SPI) with daisy chain capability allows flexible
device configuration and detailed fault reporting to an external controller. The feature differences of the SPI
and HW variants can be found in the device comparison section. The SPI interface is available in two device
variant choices, as stated below:
a. SPI (S) variant - The power supply for the digital block is provided by an internal LDO regulator sourced
from VM supply. The nSLEEP pin is a high impedance input pin.
b. SPI (P) variant - This allows for an external supply input to the digital block of the device through a VDD
pin. The nSLEEP pin is replaced by this VDD supply pin. This prevents device reset (brown out) during a
VM under voltage condition.
The DRV824x family of devices provide a load current sense output using current mirrors on the high-side
power MOSFETs. The IPROPI pin sources a small current that is proportional to the current in the high-side
MOSFETs (current sourced out of the OUTx pin). This current can be converted to a proportional voltage using
an external resistor (RIPROPI). Additionally, the devices also support a fixed off-time PWM chopping scheme for
limiting current to the load. The current regulation level can be configured through the ITRIP function.
A variety of protection features and diagnostic functions are integrated into the device. These include supply
voltage monitors (VMOV & VMUV), , off-state (Passive) diagnostics (OLP), on-state (Active) diagnostics (OLA) -
SPI variant only, overcurrent protection (OCP) for each power FET and over-temperature shutdown (TSD). Fault
conditions are indicated on the nFAULT pin. The SPI variant has additional communication protection features
such as frame errors and lock features for configuration register bits and driver control bits.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 29

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

8.2 Functional Block Diagram

8.2.1 HW Variant
High Side load to VM Low Side load to GND Full Bridge load
(Independent mode) (Independent mode) (PH/EN or PWM mode)

VM VM
PSM Gate Driver
VCP VVCP ISNS1

HS LOAD
0.1 μF Charge
Pump
VDD HS
Internal OUT1
GND LDO & Bias VDD

LS LOAD
Supply
Monitors LS
VDD GND
Oscillator
DRVOFF Thermal Shut Down (TSD)

FB LOAD
Over Current Protection (OCP)

Digital Core
nSLEEP Off-state Diagnostics (OLP)

Digital IOs VM
EN/IN1 Gate Driver
VVCP ISNS2

HS LOAD
PH/IN2
HS
OUT2
VDD

LS LOAD
MODE
LS
ITRIP GND
Impedance
SR Estimator RnFAULT
nFAULT
DIAG
ISNS1 IPROPI


ISNS2
RIPROPI

Figure 8-1. Functional Block Diagram - HW Variant

8.2.2 SPI Variant

There are two variants for the SPI interface - SPI (S) variant and SPI (P) variant as shown below.

30 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

High Side load to VM Low Side load to GND Full Bridge load
(Independent mode) (Independent mode) (PH/EN or PWM mode)

VM VM
PSM Gate Driver
VCP VVCP ISNS1

HS LOAD
0.1 μF
Charge
Pump
VDD HS
Internal OUT1
GND LDO & Bias VDD

LS LOAD
Supply
Monitors LS
VDD GND
Oscillator
DRVOFF

FB LOAD
Thermal Shut Down (TSD)
Over Current Protection (OCP)

Digital Core
nSLEEP Load Diagnostics (OLP & OLA)
VM
EN/IN1 Gate Driver
ISNS2

HS LOAD
VVCP
PH/IN2
HS
VDD OUT2
VDD
Digital IOs

LS LOAD
nSCS
LS
GND
SDI RnFAULT
nFAULT
SCLK
ISNS1 IPROPI
SDO

ISNS2
RIPROPI

Figure 8-2. Functional Block Diagram - SPI (S) Variant

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 31

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

High Side load to VM Low Side load to GND Full Bridge load
(Independent mode) (Independent mode) (PH/EN or PWM mode)

VM VM
PSM Gate Driver
VCP VVCP ISNS1

HS LOAD
0.1 μF
Charge
Pump
VDD HS
Internal OUT1
GND LDO & Bias VDD

LS LOAD
Supply
Monitors LS
VDD GND
Oscillator
DRVOFF

FB LOAD
Thermal Shut Down (TSD)
Over Current Protection (OCP)

Digital Core
nSLEEP Load Diagnostics (OLP & OLA)
VM
EN/IN1 Gate Driver
ISNS2

HS LOAD
VVCP
PH/IN2
HS
VDD OUT2
VDD
Digital IOs

LS LOAD
nSCS
LS
GND
SDI RnFAULT
nFAULT
SCLK
ISNS1 IPROPI
SDO

ISNS2
RIPROPI

Figure 8-3. Functional Block Diagram - SPI (P) Variant

32 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

8.3 Feature Description

8.3.1 External Components
Section 8.3.1.1 and Section 8.3.1.2 contain the recommended external components for the device.
8.3.1.1 HW Variant
Table 8-1. External Components Table for HW Variant
Component PIN Recommendation
CVM1 VM 0.1 µF, low ESR ceramic capacitor to GND rated for VM
Local bulk capacitor to GND, 10 µF or higher, rated for VM to handle load transients. Refer the
CVM2 VM
section on bulk capacitor sizing.
Typically 500 - 5000 Ω 0.063 W resistor to GND, depending on the controller ADC dynamic range.
RIPROPI IPROPI
Pin can be shorted to GND if ITRIP and IPROPI function is not needed.
Optional 10 - 100nF, 6.3 V capacitor to GND to slow down the ITRIP regulation loop. Refer Over
CIPROPI IPROPI
Current Protection (OCP) section.
RnFAULT nFAULT Typically 1KΩ - 10 KΩ, 0.063 W pull-up resistor to controller supply.
RMODE MODE Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer MODE table.
RSR SR Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer SR section.
RITRIP ITRIP Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer ITRIP table.
RDIAG DIAG Open or short to GND or 0.063 W 10% resistor to GND depending on setting. Refer DIAG section.

8.3.1.2 SPI Variant

Table 8-2. External Components Table for SPI Variant
Component PIN Recommendation
CVM1 VM 0.1 µF, low ESR ceramic capacitor to GND rated for VM
Local bulk capacitor to GND, 10 µF or higher, rated for VM to handle load transients. Refer the
CVM2 VM
section on bulk capacitor sizing.
Typically 500 - 5000 Ω 0.063 W resistor to GND, depending on the controller ADC dynamic range.
RIPROPI IPROPI
Pin can be shorted to GND if ITRIP and IPROPI function is not needed.
Optional 10 - 100nF, 6.3 V capacitor to GND to slow down the ITRIP regulation loop. Refer Over
CIPROPI IPROPI
Current Protection (OCP) section.
Typically 1KΩ - 10 KΩ, 0.063 W pull-up resistor to controller supply. If nFAULT signaling is not
RnFAULT nFAULT
used, this pin can be short to GND or left open.
CVDD VDD 0.1 µF, 6.3 V, low ESR ceramic capacitor to GND. This is applicable for the SPI (P) variant only.

8.3.2 Bridge Control

The DRV824x-Q1 family of devices provides three separate modes to support different control schemes with the
EN/IN1 and PH/IN2 pins. The control mode is selected through the MODE setting. MODE is a 3-level setting
based on the MODE pin for the HW variant or S_MODE bits in the CONFIG3 register for the SPI variant as
summarized in Table 8-3:
Table 8-3. Mode table
MODE pin S_MODE bits Device Mode Description
full-bridge mode where EN/IN1 is the PWM input,
RLVL1OF3 2'b00 PH/EN mode
PH/EN2 is the direction input
RLVL2OF3 2'b01 Independent mode Independent control for 2 half-bridges
full-bridge mode where EN/IN1 and PH/EN2 control
RLVL3OF3 2'b10, 2b'11 PWM mode
the PWM respectively depending on the direction

In the HW variant, MODE pin is latched during device initialization following power-up or wake-up from sleep.
Update during operation is blocked.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 33

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

In the SPI variant of the device, the mode setting can be changed anytime the SPI communication is available by
writing to the S_MODE bits. This change is immediately reflected.
The inputs can accept static or pulse-width modulated (PWM) voltage signals for either 100% or PWM drive
modes. The device input pins can be powered before VM is applied. By default, the nSLEEP and DRVOFF
pins have an internal pull-down and pull-up resistor respectively, to ensure the outputs are Hi-Z if no inputs are
present. Both the EN/IN1 and PH/IN2 pins also have internal pull down resistors. The sections below show the
truth table for each control mode.
The device automatically generates the optimal dead-time needed during transitioning between the high-side
and low-side FET on the switching half-bridge. This timing is based on internal FET gate-source voltage
feedback. No external timing is required. This scheme ensures minimum dead time, while guaranteeing no
shoot-through current.

Note
1. The SPI variant also provides additional control through the SPI_IN register bits. Refer to -
Register - Pin control.
2. For the SPI (P) variant, ignore the nSLEEP column in the control table as there is no nSLEEP pin.
Internally, nSLEEP = 1, always. The control table is valid when VDD > VDDPOR level.

8.3.2.1 PH/EN mode

In this mode, the two half-bridges are configured to operate as a full-bridge. EN/IN1 is the PWM input and
PH/IN2 is the direction input. For load illustration, refer the Load Summary section.
Table 8-4. Control table - PH/EN mode
nSLEEP DRVOFF EN/IN1 PH/IN2 OUT1 OUT2 IPROPI Device State
0 X X X Hi-Z Hi-Z No current SLEEP
1 1 0 0 Hi-Z Hi-Z No current STANDBY
1 1 1 0
1 1 0 1 Refer Off-state diagnostics table No current STANDBY
1 1 1 1
1 0 0 X H H ISNS1 or ISNS2(1) ACTIVE
1 0 1 0 L(2) H ISNS2 ACTIVE
1 0 1 1 H L(2) ISNS1 ACTIVE

(1) Current sourcing out of the device (VM → OUTx → Load)

(2) If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "H" for a fixed time

8.3.2.2 PWM mode

In this mode, the two half-bridges are configured to operate as a full-bridge. EN/IN1 provides the PWM input
in one direction, while PH/IN2 provides the PWM in the other direction. For load illustration, refer the Load
Summary section.
Table 8-5. Control table - PWM mode
nSLEEP DRVOFF EN/IN1 PH/IN2 OUT1 OUT2 IPROPI Device State
0 X X X Hi-Z Hi-Z No current SLEEP
1 1 0 0 Hi-Z Hi-Z No current STANDBY
1 1 1 0 No current STANDBY
1 1 0 1 Refer Off-state diagnostics table No current STANDBY
1 1 1 1 No current STANDBY
1 0 0 0 H H ISNS1 or ISNS2(1) ACTIVE
1 0 0 1 L(2) H ISNS2 ACTIVE
1 0 1 0 H L(2) ISNS1 ACTIVE

34 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

Table 8-5. Control table - PWM mode (continued)

nSLEEP DRVOFF EN/IN1 PH/IN2 OUT1 OUT2 IPROPI Device State
1 0 1 1 Hi-Z Hi-Z No current STANDBY

(1) Current sourcing out of device (VM → OUTx → Load)

(2) If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "H" for a fixed time

For the SPI variant, by setting the PWM_EXTEND bit in the CONFIG2 register, there are additional Hi-Z states
that are possible, when a forward ([EN/IN1 PH/IN2] = [1 0]) or reverse ([EN/IN1 PH/IN2] = [0 1]) command is
followed by a Hi-Z command ([EN/IN1 PH/IN2] = [1 1]). In this condition of Hi-Z (coasting), only the half-bridge
involved with the PWM is Hi-Z, while the HS FET on the other half-bridge is kept ON. The determination on
which half-bridge to Hi-Z is made based on the previous cycle. This is summarized in Table 8-6.
Table 8-6. PWM EXTEND table (PWM_EXTEND bit = 1'b1)
PREVIOUS STATE CURRENT STATE
Device State Transition
OUT1 OUT2 OUT1 OUT2 IPROPI
Hi-Z Hi-Z Hi-Z Hi-Z No current Remains in STANDBY, no change
H H Hi-Z Hi-Z No current ACTIVE to STANDBY
L H Hi-Z H ISNS2 ACTIVE to STANDBY
H L H Hi-Z ISNS1 ACTIVE to STANDBY

Note
For the pre-production samples, the truth table is modified as shown in Table 8-7:

Table 8-7. Control Table Differences - PWM Mode in Pre-Production Samples

nSLEEP DRVOFF EN/IN1 PH/IN2 OUT1 OUT2 IPROPI Device State
1 0 1 1 H H ISNS1 or ISNS2 ACTIVE
1 0 0 0 Hi-Z Hi-Z No current STANDBY

With this change, as an example, the PWM cycle for a forward → brake (HS recirculation) → forward, inputs will
be as follows:
• Pre-production samples: [EN/IN1 PH/IN2] = [1 0] → [1 1] → [1 0]
• Final product: [EN/IN1 PH/IN2] = [1 0] → [0 0] → [1 0]
8.3.2.3 Independent mode
In this mode, the two half-bridges are configured to be used as two independent half-bridges. The Table 8-8
shows the logic table for bridge control. For load illustration, refer the Load Summary section.
Table 8-8. Control table - Independent mode
nSLEEP DRVOFF EN/IN1 PH/IN2 OUT1 OUT2 IPROPI Device State
0 X X X Hi-Z Hi-Z No current SLEEP
1 1 0 0 Hi-Z Hi-Z No current STANDBY
1 1 1 0 No current STANDBY
1 1 0 1 Refer Off-state diagnostics table No current STANDBY
1 1 1 1 No current STANDBY
1 0 0 0 L L No current ACTIVE
1 0 0 1 L H(2) ISNS2(1) ACTIVE
1 0 1 0 H(2) L ISNS1(1) ACTIVE
1 0 1 1 H(2) H(2) ISNS1 + ISNS2(1) ACTIVE

For the SPI variant, it is possible to have independent Hi-Z control of both half-bridges through equivalent bits,
S_DRVOFF & S_DRVOFF2 in the SPI_IN register, when the SPI_IN register has been unlocked. Table 8-9

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 35

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

shows the logic table for bridge control using the pin & register combined inputs. Refer to - Register - Pin control
for details on the combined inputs shown in Table 8-9.
Table 8-9. Control table - Independent mode for SPI variant, when SPI_IN is unlocked
DRVOFF1 DRVOFF2 EN_IN1 PH_IN2
nSLEEP OUT1 OUT2 IPROPI Device State
combined combined combined combined
0 X X X X Hi-Z Hi-Z No current SLEEP
1 1 1 0 0 Hi-Z Hi-Z No current STANDBY
1 1 1 1 0 No current STANDBY
1 1 1 0 1 Refer Off-state diagnostics table No current STANDBY
1 1 1 1 1 No current STANDBY
1 1 0 X 0 Hi-Z L No current ACTIVE
1 1 0 X 1 Hi-Z H(2) ISNS2(1) ACTIVE
1 0 1 0 X L Hi-Z No current ACTIVE
1 0 1 1 X H(2) Hi-Z ISNS1(1) ACTIVE
1 0 0 0 0 L L No current ACTIVE
1 0 0 0 1 L H(2) ISNS2(1) ACTIVE
1 0 0 1 0 H(2) L ISNS1(1) ACTIVE
ISNS1 +
1 0 0 1 1 H(2) H(2) ACTIVE
ISNS2(1)

(1) Current sourcing out of device (VM → OUTx → Load)

(2) If internal ITRIP regulation is enabled and ITRIP level is reached, then OUTx is forced "L" for a fixed time

In this mode, the device behavior is as listed below:

• Load current can be sensed only for current from VM → OUTx → Load. So current sense is not possible for
high-side loads
• The current on IPROPI pin is the sum of the high-side sense current from both the half-bridges. This limits the
ITRIP current regulation feature as a combined current regulation, rather than as truly independent.
• Slew rate configurability is limited for low-side recirculation (low-side loads)
• Active state open load diagnostics (OLA) is possible only for high-side loads
• For the HW variant, it is NOT possible to have independent Hi-Z control of each half-bridge. Asserting
DRVOFF pin high will Hi-Z both the half-bridges.
8.3.2.4 Register - Pin Control - SPI Variant Only
The SPI variant allows control of the bridge through the specific register bits, S_DRVOFF, S_DRVOFF2,
S_EN_IN1, S_PH_IN2 in the SPI_IN register, provided the SPI_IN register has been unlocked. The user
can unlock this register by writing the right combination to the SPI_IN_LOCK bits in the COMMAND register.
Additionally, the user can configure between an AND / OR logic combination of each of external input pin with
their equivalent register bit in the SPI_IN register. This logical configuration is done through the equivalent
selects bits in the CONFIG4 register:
• DRVOFF_SEL, EN_IN1_SEL and PH_IN2_SEL
The control of the output is similar to the truth tables described in the section before, but with these logically
combined inputs. These combined inputs are listed as follows:
• Combined input = Pin input OR equivalent SPI_IN register bit, if equivalent CONFIG4 select bit = 1'b0
• Combined input = Pin input AND equivalent SPI_IN register bit, if equivalent CONFIG4 select bit = 1'b1
• In Independent mode:
– DRVOFF2 combined = DRVOFF pin OR S_DRVOFF2 bit, if DRVOFF_SEL bit = 1'b0
– DRVOFF2 combined = DRVOFF pin AND S_DRVOFF2 bit, if DRVOFF_SELbit = 1'b1
Note that external nSLEEP pin is still needed for sleep function.
This logical combination offers more configurability to the user as shown in the table below.

36 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

Table 8-10. Register - Pin Control Examples

CONFIG4: xxx_SEL
Example PIN status SPI_IN Bit Status Comment
Bit

DRVOFF as Either DRVOFF pin = 1 or S_DRVOFF bit = 1

DRVOFF_SEL = 1’b0 DRVOFF active S_DRVOFF active
redundant shutoff will shutoff the output

Pin only control DRVOFF_SEL = 1’b1 DRVOFF active S_DRVOFF = 1'b1 Only DRVOFF pin function is available

PH_IN2_SEL bit = PH/IN2 - short to PH (direction) will be controlled by the

Register only control S_PH_IN2 active
1’b0 GND or float register bit alone

Note
This logical combination is NOT supported in the pre-production samples. In this case, when the
SPI_IN register is unlocked, the output is controlled from the equivalent register bits and the input
pins are ignored. In other words, if SPI_IN unlocked, xxx_combined = S_xxx register bits, else
xxx_combined = Input pin.

8.3.3 Device Configuration

This section describes the various device configurations to enable the user to configure the device to suit their
use case.
8.3.3.1 Slew Rate (SR)
The SR pin (HW variant) or S_SR bits in the CONFIG3 register (SPI variant) determines the slew rate of
the driver. This enables the user to optimize the PWM switching losses while meeting the EM conformance
requirements. For the HW variant, SR is a 6-level setting as summarized in the table below. SPI variant has
additional 2 levels.
Table 8-11. SR Table
SR Pin S_SR Register Bits SRLSOFF, SRLSON [V/µsec](1) SRHSOFF [V/µsec](2) SRHSON [V/µsec](2)
RLVL2OF6 3'b000 1.2 40 10
Not available 3'b001 4 40 10
Not available 3'b010 6.7 40 10
RLVL3OF6 3'b011 11.4 15 10
RLVL4OF6 3'b100 17 20 10
RLVL1OF6 3'b101 22 26 10
RLVL6OF6 3'b110 32 37 10
RLVL5OF6 3'b111 41 48 10

(1) Applicable for high-side recirculation

(2) Applicable for low-side recirculation (only in the Independent mode operation using low-side load)

Note
The SPI variant also offers an optional spread spectrum clocking (SSC) feature that spreads the
internal oscillator frequency +/- 12% around its mean with a period triangular function of ~1.3 MHz to
reduce emissions at higher frequencies.

In the HW variant, the SR pin is latched during device initialization following power-up or wake-up from sleep.
Update during operation is blocked. Also there is no spread spectrum clocking (SSC) feature.
In the SPI variant, the slew rate setting can be changed at any time when SPI communication is available by
writing to the S_SR bits. This change is immediately reflected.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 37

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

Note
For the pre-production samples, the SR settings are as shown in Table 8-12 the table below. Also, in
the HW variant, SSC feature is always enabled.

Table 8-12. Pre-Production Samples - SR Table

SR Pin S_SR Register Bits SRLSOFF, SRLSON [V/µsec](1) SRHSOFF [V/µsec](2) SRHSON [V/µsec](2)

RLVL1OF6 3'b000 23 23 8

RLVL2OF6 3'b001 1.6 1.6 1.6

RLVL3OF6 3'b010 33 33 8

RLVL4OF6 3'b011 38 38 8

RLVL5OF6 3'b100 43 43 8

RLVL6OF6 3'101 28 28 8

Not available 3'b110 18 18 8

Not available 3'b111 12 12 8

8.3.3.2 IPROPI
The device integrates a current sensing feature with a proportional analog current output on the IPROPI pin that
can be used for load current regulation. This eliminates the need of an external sense resistor or sense circuitry
reducing system size, cost, and complexity.
The device senses the load current by using a shunt-less high-side current mirror topology. This way the device
can only sense an uni-directional high-side current from VM → OUTx → Load through the high-side FET when
it is fully turned ON (linear mode). The IPROPI pin outputs an analog current proportional to this sensed current
scaled by AIPROPI as follows:
IIPROPI = (IHS1 + IHS2) / AIPROPI
The IPROPI pin must be connected to an external resistor (RIPROPI) to ground in order to generate a proportional
voltage VIPROPI. This allows for the load current to be measured as a voltage-drop across the RIPROPI resistor
with an analog to digital converter (ADC). The RIPROPI resistor can be sized based on the expected load current
in the application so that the full range of the controller ADC is utilized.
The current expressed on IPROPI is the sum of the currents flowing out of the OUTx pins from VM. This implies
that:
• In full-bridge operation using PWM or PH/EN mode, the current expressed on IPROPI pin is always from one
of the half-bridges that is sourcing the current from VM to the load.
• In independent mode, the current expressed on IPROPI pin could be from either half-bridges or both of them.
It is not possible to observe only one half-bridge current independently.
8.3.3.3 ITRIP Regulation
The device offers an optional internal load current regulation feature using fixed TOFF time method. This is done
by comparing the voltage on the IPROPI pin against a reference voltage determined by ITRIP setting. TOFF time
is fixed at 30 µsec for HW variant, while it is configurable between or 20 to 50 µsec for the SPI variant using
TOFF_SEL bits in the CONFIG3 register.
The ITRIP regulation, when enabled, comes into action only when the HS FET is enabled and current sensing is
possible. In this scenario, when the voltage on the IPROPI pin exceeds the reference voltage set by the ITRIP
setting, the internal current regulation loop forces the following action:
• In PH/EN or PWM mode, OUT1 = H, OUT2 = H (high-side recirculation) for the fixed TOFF time
– Cycle skipping: Due to minimum duty cycle limitations (especially at low slew rate settings and high VM),
load current will contiue to increase even with ITRIP regulation. In order to prevent this current walk away,
a cycle skipping scheme is implemented, where, if IOUT sensed is still greater than ITRIP at the end of

38 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

TOFF time, then the recirculation time is extended by an additional TOFF period. This recirculation time
addition will continue till IOUT sensed is less than ITRIP at the end of the TOFF period.
• In Independent mode, If OUTx = H, then toggle OUTx = L for the fixed TOFF time, else no action on OUTx

Note
The user inputs always takes precedence over the internal control. That means that if the inputs
change during the TOFF time, the remainder of the TOFF time is ignored and the outputs will follow
the inputs as commanded.

IPROPI ISNS High Side Current VM

Sense
RIPROPI
V(IPROPI)

ITRIP_CMP
ITRIP Impedance Estimator V(ITRIP) OUTx
(HW variant) DAC

RITRIP

SPI (SPI variant) Digital Core GND

Figure 8-4. ITRIP Implementation

Current limit is set by the following equation:

ITRIP regulation level = VITRIP / RIPROPI X AIPROPI (2)

ITRIP regula
on ac ve
ITRIP
IOUT

VOUT1
VOUT2

EN/IN1
tOFF tOFF tOFF

PH/IN2
E.g. PH/EN mode
Figure 8-5. Fixed TOFF ITRIP Current Regulation

In Independent mode, since ITRIP regulation is based on summation of the two half-bridge currents on IPROPI
pin, it is not possible to have completely independent current regulation for the two half-bridges simultaneously.
The ITRIP comparator output (ITRIP_CMP) is ignored during output slewing to avoid false triggering of the
comparator output due to current spikes from the load capacitance. Additionally, in the event of transition from
low-side recirculation, an additional blanking time tBLANK is needed for the sense loop to stabilize before the
ITRIP comparator output is valid.
ITRIP is a 6-level setting for the HW variant. The SPI variant offers two more settings. This is summarized in the
table below:

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 39

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

Table 8-13. ITRIP Table

ITRIP Pin S_ITRIP Register Bits VITRIP [V]
RLVL1OF6 3'b000 Regulation Disabled
RLVL2OF6 3'b001 1.18
Not available 3'b010 1.41
Not available 3'b011 1.65
RLVL3OF6 3'b100 1.98
RLVL4OF6 3'b101 2.31
RLVL5OF6 3'b110 2.64
RLVL6OF6 3'b111 2.97

In the HW variant of the device, the ITRIP pin changes are transparent and changes are reflected immediately.
In the SPI variant of the device, the ITRIP setting can be changed at any time when SPI communication is
available by writing to the S_ITRIP bits. This change is immediately reflected in the device behavior.
SPI variant only - If the ITRIP regulation levels are reached, the ITRIP_CMP bit in the STATUS1 register is set.
There is no nFAULT pin indication. This bit can be cleared with a CLR_FLT command.

Note
For pre-production samples, the ITRIP settings are as shown in the table below.

Table 8-14. Pre-Production Samples - ITRIP Table

ITRIP Pin S_ITRIP Register Bits VITRIP [V]
RLVL1OF6 3'b000 Regulation Disabled
RLVL2OF6 3'b001 1.65
RLVL3OF6 3'b010 1.98
RLVL4OF6 3'b011 2.31
RLVL5OF6 3'b100 2.64
RLVL6OF6 3'b101, 3'b110, 3'b111 2.97

8.3.3.4 DIAG
The DIAG is a pin (HW variant) or register (SPI variant) setting that is used in both ACTIVE and STANDBY
operation of the device, as follows:
• STANDBY state
– In PH/EN or PWM modes: Enable or disable Off-state diagnostics (OLP).
– Enable or disable Off-state diagnostics (OLP), as well as select the OLP combinations when enabled.
Refer to the tables in the Off-state diagnostics (OLP) section for details on this.
• ACTIVE state
– Mask ITRIP regulation function if the load type is indicated as high-side load.
– SPI variant only - Mask active open load detection (OLA) if the load type is indicated as low-side. load
– HW variant only - Configure fault reaction between retry and latch settings
8.3.3.4.1 HW variant
For the HW variant, the DIAG pin is a 6-level setting. Depending on the mode, its configurations are
summarized in the table below.
Table 8-15. DIAG table for the HW variant, PH/EN or PWM mode
STANDBY state ACTIVE state
DIAG pin
Off-state diagnostics Fault reaction

RLVL1OF6 Disabled Retry

All other levels Enabled(1) Latch

40 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

Table 8-16. DIAG table for the HW variant, Independent mode

STANDBY state ACTIVE state
DIAG pin
Off-state diagnostics Load Configuration Fault reaction IPROPI / ITRIP

RLVL1OF6 Disabled Low-side load Retry Available

RLVL2OF6 Enabled(1) Low-side load Latch Available

RLVL3OF6 Enabled(1) High-side load Latch Disabled

RLVL4OF6 Enabled(1) High-side load Retry Disabled

RLVL5OF6 Disabled Low-side load Latch Available

RLVL6OF6 Enabled(1) Low-side load Retry Available

(1) Refer to the tables in the Off-state diagnostics (OLP) section for combination details

Note
HW variant only - Option to disable off-state diagnostics for a high-side load use case is not
supported. In this case, setting DRVOFF pin high and IN pin low is only way to disable off-state
diagnostics.

In the HW variant, the DIAG pin is latched during device initialization following power-up or wake-up from sleep.
Update during operation is blocked.
8.3.3.4.2 SPI variant
For the SPI variant, S_DIAG is a 2-bit setting in the CONFIG2 register. Depending on the mode, its
configurations are summarized in the table below.
Table 8-17. DIAG table for the SPI variant, PH/EN or PWM mode
STANDBY state ACTIVE state
S_DIAG bits
Off-state diagnostics On-state diagnostics

2'b00 Disabled Available

2'b01, 2'b10, 2'b11 Enabled(1) Available

Table 8-18. DIAG table for the SPI variant, Independent mode
STANDBY state ACTIVE state
S_DIAG bits
Off-state diagnostics Load Configuration On-state diagnostics IPROPI / ITRIP
2'b00 Disabled Low-side load Disabled Available
2'b01 Enabled(1) Low-side load Disabled Available
2'b10 Disabled High-side load Available Disabled
2'b11 Enabled(1) High-side load Available Disabled

(1) Refer to the tables in the Off-state diagnostics (OLP) section for combination details

In the SPI variant of the device, the settings can be changed anytime when SPI communication is available by
writing to the S_DIAG bits. This change is immediately reflected.
8.3.4 Protection and Diagnostics
The driver is protected against over-current and over-temperature events to ensure device robustness.
Additionally, the device also offers load monitoring (on-state and off-state), over/ under voltage monitoring on
VM pin to signal any unexpected voltage conditions. Fault signaling is done through a low-side open drain
nFAULT pin which gets pulled to GND by InFAULT_PD current on detection of a fault condition. Transition to SLEEP
state automatically de-asserts nFAULT.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 41

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

Note
In the SPI variant, nFAULT pin logic level is the inverted copy of the FAULT bit in the FAULT
SUMMARY register. Only exception is when off-state diagnostics are enabled and SPI_IN register
is locked (Refer OLP section) .

For the SPI variant, whenever nFAULT is asserted low, the device logs the fault into the FAULT SUMMARY and
STATUS registers. These registers can be cleared only by
• CLR FLT command or
• SLEEP command through the nSLEEP pin
It is possible to get all the useful diagnostic information for periodic software monitoring in a single 16 bit SPI
frame by:
• Reading the STATUS1 register during ACTIVE state
• Reading the STATUS2 register during STANDBY state
All the diagnosable fault events can be uniquely identified by reading the STATUS registers.
8.3.4.1 Over Current Protection (OCP)
• Device state: ACTIVE
• Mechanism & thresholds: An analog current limit circuit on each MOSFET limits the peak current out of the
device even in hard short circuit events. If the output current exceeds the overcurrent threshold, IOCP, for
longer than tOCP, then an over current fault is detected.
• Action:
– nFAULT pin is asserted low
– Reaction is based on mode selection:
• PH/EN or PWM mode - Both OUTx is Hi-Z
• Independent mode - The affected half-bridge OUTx is Hi-Z
– For a short to GND fault (over current detected on the high-side FET), the IPROPI pin continues to be
pulled up to VIPROPI_LIM even if the FET has been disabled. For the HW variant, this helps differentiate a
short to GND fault during ACTIVE state from other fault types, as the IPROPI pin is pulled high while the
nFAULT pin is asserted low.
• Reaction configurable between latch setting and retry setting based on tRETRY and tCLEAR
• User can add a small 6.3V capacitor in the range of 10 nF to 100 nF on the IPROPI pin to avoid a race
condition with ITRIP regulation in case of a load short condition when ITRIP regulation is enabled.
– In case of a load short where there is enough inductance in the short, ITRIP regulation could trigger ahead
of the OCP detection, resulting in the device missing the OCP detection. To ensure that OCP detection
wins this race condition, a small capacitor (10 nF - 100 nF) on the IPROPI pin is recommended. This
capacitance slows down the ITRIP regulation loop enough to allow the OCP detection circuit to work as
intended.
The SPI variant offers configurable IOCP levels and tOCP filter times. Refer CONFIG4 register for these settings.
8.3.4.2 Over Temperature Protection (TSD)
• Device state: STANDBY, ACTIVE
• Mechanism & thresholds: The device has several temperature sensors spread around the die. If any of the
sensors detect an over temperature event, set by TTSD for a time greater than tTSD, then an over temperature
fault is detected.
• Action:
– nFAULT pin is asserted low
– Both OUTx is Hi-Z
– IPROPI pin is Hi-Z
• Reaction configurable between latch setting and retry setting based on THYS and tCLEAR_TSD

42 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

8.3.4.3 Off-State Diagnostics (OLP)

The user can determine the impedance on the OUTx node using off-state diagnostics in the STANDBY state
when the power FETs are off. With this diagnostics, it is possible to detect the following fault conditions passively
in the STANDBY state:
• Output short to VM or GND < 100 Ω
• Open load > 1K Ω for full-bridge load or low-side load
• Open load > 10K Ω for high-side load, VM = 13.5 V

Note
It is NOT possible to detect a load short with this diagnostic. However, the user can deduce this
logically if an over current fault (OCP) occurs during ACTIVE operation, but OLP diagnotics do not
report any fault in the STANDBY state. Occurrence of both OCP in the ACTIVE state and OLP in the
STANDBY state would imply a terminal short (short on OUT node).

• The user can configure the following combinations

– Internal pull up resistor (ROLP_PU) on OUTx
– Internal pull down resistor (ROLP_PD) on OUTx
– Comparator reference level
– Comparator input selection (OUT1 or OUT2)
• This combination is determined by the controller inputs (pins only for the HW variant) or equivalent bits in the
SPI_IN register for the SPI variant if the SPI_IN register has been unlocked.
• HW variant - When off-state diagnostics are enabled, comparator output (OLP_CMP) is available on nFAULT
pin.
• SPI variant - The off-state diagnostics comparator output (OLP_CMP) is available on OLP_CMP bit in
STATUS2 register. Additionally, if the SPI_IN register has been locked, this comparator output is also
available on the nFAULT pin when off-state diagnostics are enabled.
• The user is expected to toggle through all the combinations and record the comparator output after its output
is settled.
• Based on the input combinations and comparator output, the user can determine if there is a fault on the
output.
Internal
5V

VM

ROLP_PU ROLP_PU

D1 D1
OUT1 OUT2
Filter Filter
ROLP_PD
ROLP_PD RHIZ D2 D2 RHIZ

GND
OLP_CMP
Output on nFAULT pin / register VOLP_REFH REF Voltage propor
onal
VOLP_REFL to Internal 5V

PIN / register control

Figure 8-6. Off-State Diagnostics for full-bridge Load (PH/EN or PWM Mode)

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 43

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

The OLP combinations and truth table for a no fault scenario vs. fault scenario for a full-bridge load in PH/EN or
PWM modes is shown in Table 8-19.
Table 8-19. Off-State Diagnostics Table - PH/EN or PWM Mode (full-bridge)
User Inputs OLP Set-Up OLP CMP Output

Output GND
nSLEEP DRVOFF EN/IN1 PH/IN2 OUT1 OUT2 CMP REF Normal Open VM Short
selected Short

1 1 1 0 ROLP_PU ROLP_PD VOLP_REFH OUT1 L H L H

1 1 0 1 ROLP_PU ROLP_PD VOLP_REFL OUT2 H L L H

1 1 1 1 ROLP_PD ROLP_PU VOLP_REFL OUT2 H H L H

The OLP combinations and truth table for a no fault scenario vs. fault scenario for a low-side load in Independent
mode is shown in Table 8-20.
Table 8-20. Off-State Diagnostics Table for Low-Side Load - Independent Mode
User Inputs OLP Set-Up OLP_CMP Output

DIAG S_DIAG CMP Output

nSLEEP DRVOFF EN/IN1 PH/IN2 OUT1 OUT2 Normal Open Short
pin bits REF selected

LVL2, don't VOLP_REF

2'b01 1 1 1 ROLP_PU Hi-Z OUT1 L H H
LVL6 care H

LVL3, don't VOLP_REF

2'b11 1 1 1 ROLP_PD Hi-Z OUT1 L L H
LVL4 care L

LVL2, VOLP_REF
2'b01 1 1 0 1 Hi-Z ROLP_PU OUT2 L H H
LVL6 H

LVL3, VOLP_REF
2'b11 1 1 0 1 Hi-Z ROLP_PD OUT2 L L H
LVL4 L

The OLP combinations and truth table for a no fault scenario vs. fault scenario for a high-side load in
Independent mode is shown in Table 8-21.
Table 8-21. Off-State Diagnostics Table for High-Side Load - Independent Mode
User Inputs OLP Set-Up OLP_CMP Output

DIAG S_DIAG CMP Output

nSLEEP DRVOFF EN/IN1 PH/IN2 OUT1 OUT2 Normal Open Short
pin bits REF selected

LVL2, don't VOLP_REF

2'b01 1 1 1 ROLP_PU Hi-Z OUT1 H H L
LVL6 care H

LVL3, don't VOLP_REF

2'b11 1 1 1 ROLP_PD Hi-Z OUT1 H L L
LVL4 care L

LVL2, VOLP_REF
2'b01 1 1 0 1 Hi-Z ROLP_PU OUT2 H H L
LVL6 H

LVL3, VOLP_REF
2'b11 1 1 0 1 Hi-Z ROLP_PD OUT2 H L L
LVL4 L

Note
For the pre-production samples, it is NOT possible to differentiate between an open fault and a load
short in the Independent mode.

8.3.4.4 On-State Diagnostics (OLA) - SPI Variant Only

• Device state: ACTIVE - high-side recirculation

44 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

• Mechanism and threshold: On-state diagnostics (OLA) can detect an open load detection in the ACTIVE state
during high-side recirculation. This includes high-side load connected directly to VM or through a high-side
FET on the other half-bridge. During a PWM switching transition, the inductive load current re-circulates into
VM through the HS body diode when the LS FET is turned OFF. The device looks for a voltage spike on
OUTx above VM during the brief dead time, before the HS FET is turned ON. To observe the voltage spike,
this load current needs to be higher than the pull down current (IPD_OLA) on the output asserted by the FET
driver. Absence of this voltage spike for "3" consecutive re-circulation switching cycles indicates a loss of load
inductance or increase in load resistance and is detected as an OLA fault.
• Action:
– nFAULT pin is asserted low
– Output - normal function maintained
– IPROPI pin - normal function maintained
• Reaction configurable between latch setting and retry setting. In retry setting, OLA fault is automatically
cleared with the detection of "3" consecutive voltage spikes during re-circulation switching cycles.
This monitoring is optional and can be disabled.

Note
OLA is not supported for low-side loads (low-side recirculation).

VM
OLA_VREF OUTx_OLA_CMP

D1

OUTx
IPD_OLA D2

GND
Figure 8-7. On-State Diagnostics

8.3.4.5 VM Over Voltage Monitor

• Device state: STANDBY, ACTIVE
• Mechanism & thresholds: If the supply voltage on the VM pin exceeds the threshold, set by VVMOV for a time
greater than tVMOV, then an VM over voltage fault is detected.
• Action:
– nFAULT pin is asserted low
– Output - normal function maintained
– IPROPI pin - normal function maintained
• Reaction configurable between retry and latch setting
In the SPI variant, this monitoring is optional and can be disabled. Also the thresholds are configurable. Refer
CONFIG1 register.
8.3.4.6 VM Under Voltage Monitor
• Device state: STANDBY, ACTIVE
• Mechanism & thresholds: If the supply voltage on the VM pin drops below the threshold, set by VVMUV for a
time greater than tVMUV, then an VM under voltage fault is detected.
• Action:

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 45

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

– nFAULT pin is asserted low

– Both OUTx is Hi-Z
– IPROPI pin is Hi-Z
• HW and SPI (S) variant: Reaction fixed to retry setting
• Only for SPI (P) variant: Reaction configurable between retry and latch setting
• Note that retry time is only dependent on recovery of VM under voltage condition and is independent of
tRETRY / tCLEAR times
8.3.4.7 Power On Reset (POR)
• Device state: ALL
• Mechanism & thresholds: If logic supply drops below VDDPOR_FALL for a time greater than tPOR, then a power
on reset will occur that will hard reset the device.
• Action:
– nFAULT pin is de-asserted
– Both OUTx is Hi-Z
– IPROPI pin is Hi-Z.
– When this supply recovers above the VDDPOR_RISE level, the device will go through a wake-up
initialization and nFAULT pin will be asserted low to notify the user on this reset (Refer Wake-up
transients).
• HW and SPI (S) variant: These thresholds translate to VMPOR_FALL and VMPOR_RISE as the logic supply is
internally derived from the VM supply
• Only for SPI (P) variant: These thresholds directly map to the VDD pin voltage (VDDPOR_FALL and
VDDPOR_RISE)
• Fault reaction: Always retry, retry time depends on the external supply condition to initiate a device wake-up
8.3.4.8 Event Priority
In the ACTIVE state, in a scenario where two or more events occur simultaneously, the device assigns control of
the driver based on the following priority table.
Table 8-22. Event Priority Table
Event Priority
User SLEEP command 1
User input: DRVOFF 2
Over temperature detection (TSD) 3
Over current detection (OCP)(1) 4
VM under voltage detection (VMUV) 5
User input: EN/IN1 and/or PH/IN2 6
Internal PWM control from ITRIP regulation 7
VM over voltage detection (VMOV)(2) 8
On-state fault detection (OLA - SPI variant only)(2) 9

(1) If the device is waiting for an OCP event to be confirmed (waiting for tOCP) when any of events with lower priority than OCP occur, then
the device may delay servicing the other events up to a maximum time of tOCP to enable detection of the OCP event.
(2) Priority is "don't care" in this case as this fault event does not cause a change in OUTx

8.4 Device Functional States

The device has three functional states:
• SLEEP
• STANDBY
• ACTIVE

46 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

SLEEP
nFAULT = H, No communica
on

1
2 2 2

ACTIVE
INIT2 STANDBY Protec on Enabled
6
INIT1 nFAULT = L nFAULT = H nFAULT = fault
3 4 5
nFAULT = H Communicaon Communicaon signaling
enabled available 7 Communicaon
available

1. nSLEEP = 1 for t > tWAKE 2. nSLEEP = 0 for t > tSLEEP

3. Power on reset 4. End of tCOM
5. CLR_FLT or HW RESET pulse from from controller & End of tREADY
6. DRVOFF = 0 & [IN1/EN IN2/PH] != [1 1], if PWM mode
7. DRVOFF = 1 or [IN1/EN IN2/PH] = [1 1], if PWM mode

Note
For pre-production samples, [IN1/EN IN2/PH] = [0 0], if PWM mode

Figure 8-8. Illustrative State Diagram

These states are described in the following section.

8.4.1 SLEEP State
This state occurs when nSLEEP pin is asserted low for a time > tSLEEP or voltage on the VDD pin is <
VDDPOR_FALL.
This is the deep sleep low power (ISLEEP) state of the device where all functions except a wake-up command are
not serviced. The drivers are in Hi-Z. The internal power supply rails (5 V and others) are powered off. nFAULT
pin is de-asserted in this state. The device can enter this state from either the STANDBY or the ACTIVE state,
when the nSLEEP pin is asserted low for time longer than tSLEEP (HW variant) or for tSLEEP_SPI (SPI (S) variant).
8.4.2 STANDBY State
The device is in this state when nSLEEP pin is asserted high or the voltage on the VDD pin is > VDDPOR_RISE
with DRVOFF = 1'b0 for all modes and additionally, in PWM mode when both IN1/EN & IN2/PH are 1'b1 [Note:
1'b0 for pre-production samples]. In this state, the device is powered up (ISTANDBY), with the driver Hi-Z and
nFAULT de-asserted. The device is ready to transition to ACTIVE state or SLEEP state when commanded so.
Off-state diagnostics (OLP), if enabled, are done in this state.
8.4.3 Wake-up to STANDBY State
The device starts transition from SLEEP state to STANDBY state
• if the nSLEEP pin goes high for a duration longer than tWAKE, or
• if VM supply > VMPOR_RISE or VDD supply > VDDPOR_RISE such that internal POR is released to indicate a
power-up.
The device goes through an initialization sequence to load its internal registers and wake-up all the blocks in the
following sequence:
• At a certain time, tCOM from wake-up, the device is capable of communication. This is indicated by asserting
the nFAULT pin low.
• This is followed by the time tREADY, when the device wake-up is complete.
• At this point, once the device receives a nSLEEP reset pulse (HW variant) or a CLR FAULT command
through SPI (SPI variant) as an acknowledgment of the wake-up from the controller, the device enters the
STANDBY state. This is indicated by the de-assertion of the nFAULT pin. The driver is held in Hi-Z till this
point.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 47

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

• From here on, the device is ready to drive the bridge based on the truth tables for the specific mode
configured.
Refer to the wake-up transients waveforms for the illustration.
8.4.4 ACTIVE State
The device is fully functional in this state with the drivers controlled by other inputs as described in prior sections.
All protection features are fully functional with fault signaling on nFAULT pin. SPI communication is available.The
device can transition into this state only from the STANDBY state.
8.4.5 nSLEEP Reset Pulse (HW Variant Only)
This is a special communication signal from the controller to the device through the nSLEEP pin available only
for the HW variant. This is used to:
• Acknowledge the nFAULT asserted during the SLEEP/ Power up transition to STANDBY state
• Clear a latched fault when the fault reaction is configured to the LATCHED setting, without forcing the device
into SLEEP or affecting any of the other functions (Equivalent to the CLR_FAULT command in the SPI
variant)
This pulse on nSLEEP must be greater than the nSLEEP deglitch time of tRESET time, but shorter than tSLEEP
time, as shown in case # 3, in Table 8-23 below.
Table 8-23. nSLEEP Timing (HW Variant Only)
Command Interpretation
Case # Window Start Time Window End Time
Clear Fault Sleep

1 0 tRESET min No No

2 tRESET min tRESET max Interdeterminate No

3 tRESET max tSLEEP min Yes No

4 tSLEEP min tSLEEP max Yes Interdeterminate

5 tSLEEP max No limit Yes Yes

tSLEEP max
tSLEEP min
tRESET max
tRESET min

Case 1
nSLEEP pulses

Case 2

Case 3

Case 4

Case 5

Window 1 Window 2 Window 3 Window 4 Window 5

me
Figure 8-9. nSLEEP Pulse Scenarios

48 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

8.5 Programming - SPI Variant Only

8.5.1 SPI Interface
The SPI variant has full-duplex, 4-wire synchronous communication that is used to set device configurations,
operating parameters, and read out diagnostic information from the device. The SPI operates in peripheral mode
and connects to a controller. The serial data input (SDI) word consists of a 16-bit word, with an 8-bit command
(A1), followed by 8-bit data (D1). The serial data output (SDO) word consists of the FAULT_SUMMARY byte
(S1), followed by a report byte (R1). The report byte is either the register data being accessed by read command
or null for a write command. The data sequence between the MCU and the SPI peripheral driver is shown in
Figure 8-10.

nSCS

A1 D1
SDI

SDO
S1 R1

Figure 8-10. SPI Data - Standard "16-bit" Frame

A valid frame must meet the following conditions:

• SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
• nSCS pin should be pulled high between words.
• When nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is placed
in the Hi-Z state.
• Data on SDO from the device is propagated on the rising edge of SCLK, while data on SDI is captured by the
device on the subsequent falling edge of SCLK.
• The most significant bit (MSB) is shifted in and out first.
• A full 16 SCLK cycles must occur for a valid transaction for a standard frame, or alternately, for a daisy chain
frame with "n" number of peripheral devices, 16 + (n x 16) SCLK cycles must occur for a valid transaction.
Else, a frame error (SPI_ERR) is reported and the data is ignored if it is a WRITE operation.
8.5.2 Standard Frame
The SDI input data word is 2 bytes long and consists of the following format:
• Command byte (first byte)
– MSB bit indicates frame type (bit B15 = 0 for standard frame).
– Next to MSB bit, W0, indicates read or write operation (bit B14, write = 0, read = 1)
– Followed by 6 address bits, A[5:0] (bits B13 through B8)
• Data byte (second byte)
– Second byte indicates data, D[7:0] (bits B7 through B0). For a read operation, these bits are typically set
to null values, while for a write operation, these bits have the data value for the addressed register.
Table 8-24. SDI - Standard Frame Format
Command Byte Data Byte
Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Data 0 W0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

The SDO output data word is 2 bytes long and consists of the following format:
• Status byte (first byte)

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 49

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

– 2 MSB bits are forced high (B15, B14 = 1)

– Following 6 bits are from the FAULT SUMMARY register (B13:B8)
• Report byte (second byte)
– The second byte (B7:B0) is either the data currently in the register being read for a read operation (W0 =
1), or, existing data in the register being written to for a write command (W0 = 0)
Table 8-25. SDO - Standard Frame Format
Status Byte Report Byte
Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
SPI_E
Data 1 1 FAULT VMOV VMUV OCP TSD D7 D6 D5 D4 D3 D2 D1 D0
RR

Note
For the pre-production samples, B8 in the above SDO format is OLA bit (not SPI_ERR as shown).

8.5.3 SPI Interface for Multiple Peripherals

Multiple devices can be connected to the controller with and without the daisy chain. For connecting a 'n' number
of devices to a controller without using a daisy chain, 'n' number of I/O resources from controller has to utilized
for nSCS pins as shown in Figure 8-11. Whereas, if the daisy chain configuration is used, then a single nSCS
line can be used for connecting multiple devices. Figure 8-12

DRV8x DRV8x
SCLK SCLK
Master Controller SDI Master Controller SDI
SPI SPI
SDO Communication SDO Communication
CS1 nSCS CS nSCS
MCLK MCLK
SPI MO SPI MO
Communication Communication
MI DRV8x MI DRV8x
SCLK SCLK
CS2
SDI SDI
SPI SPI
SDO Communication SDO Communication
nSCS nSCS

Figure 8-11. SPI Operation Without Daisy Chain Figure 8-12. SPI Operation With Daisy Chain

50 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

8.5.3.1 Daisy Chain Frame for Multiple Peripherals

The device can be connected in a daisy chain configuration to save GPIO ports when multiple devices
are communicating to the same MCU. Figure 8-13 shows the topology with waveforms, where, number of
peripherals connected in a daisy chain "n" is set to 3. A maximum of up to 63 devices can be connected in this
manner.

M-SDO SDO1 SDO2 SDO3

M-SDO SDI1 SDO1 SDI2 SDO2 SDI2 SDO3
SDI1 SDI2 SDI3 M-SDI

M-nSCS

M-SCLK

M-SDI

nSCS

HDR1 HDR2 A3 A2 A1 D3 D2 D1
SDI1

SDO1
S1 HDR1 HDR2 A3 A2 R1 D3 D2
SDI2

SDO2
S2 S1 HDR1 HDR2 A3 R2 R1 D3
SDI3

SDO3
S3 S2 S1 HDR1 HDR2 R3 R2 R1

All Address All Address

Bytes Reach Bytes Reach
Destination Destination

Status Reads Writes

Response Here Execute Here Execute Here

Figure 8-13. Daisy Chain SPI Operation

The SDI sent by the controller in this case would be in the following format (see SDI1 in Figure 8-13 ):
• 2 bytes of header (HDR1, HDR2)
• "n" bytes of command byte starting with furthest peripheral in the chain (for this example, this is A3, A2, A1)
• "n" bytes of data byte starting with furthest peripheral in the chain (for this example, this is D3, D2, D1)
• Total of 2 x "n" + 2 bytes
While the data is being transmitted through the chain, the controller receives it in the following format (see SDO3
in Figure 8-13):
• 3 bytes of status byte starting with furthest peripheral in the chain (for this example, this is S3, S2, S1)
• 2 bytes of header that were transmitted before (HDR1, HDR2)
• 3 bytes of report byte starting with furthest peripheral in the chain (for this example, this is R3, R2, R1)

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 51

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

The Header bytes are special bytes asserted at the beginning of a daisy chain SPI communication. Header
bytes must start with 1 and 0 for the two leading bits.
The first header byte (HDR1) contains information of the total number of peripheral devices in the daisy chain.
N5 through N0 are 6 bits dedicated to show the number of device in the chain as shown in Figure 8-14. Up to
63 devices can be connected in series per daisy chain connection. Number of peripheral = 0 is not permitted and
will result in a SPI_ERR flag.
The second header byte (HDR2) contains a global CLR FAULT command that will clear the fault registers of
all the devices on the rising edge of the chip select (nSCS) signal. The 5 trailing bits of the HDR2 register are
marked as SPARE (don’t care bits). These can be used by the MCU to determine integrity of the daisy chain
connection.

1 0 N5 N4 N3 N2 N1 N0
HDR1

Number of Devices in the Chain (Up to 63 max)

1 0 CLR_FLT SPARE SPARE SPARE SPARE SPARE

HDR2

Don’t Care
1 = Global CLR_FAULT
0 = Don’t Care

Figure 8-14. Header bytes

In addition, the device recognizes bytes that start with 1 and 1 for the two leading bits as a "pass" byte. These
"pass" bytes are NOT processed by the device, but they are simply transmitted out on SDO in the following byte.
When data passes through a device, it determines the position of itself in the chain by counting the number of
Status bytes it receives following by the first Header byte. For example, in this 3 device configuration, device 2 in
the chain will receive two status bytes before receiving the two header bytes.
From the two status bytes it knows that its position is second in the chain, and from HDR2 byte it knows how
many devices are connected in the chain. That way it only loads the relevant address and data byte in its buffer
and bypasses the other bits. This protocol allows for faster communication without adding latency to the system
for up to 63 devices in the chain.
The command, data, status and report bytes remain the same as described in the standard frame format.

52 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

8.6 Register Map - SPI Variant Only

This section describes the user configurable registers in the device.

Note
While the device allows register writes at any time SPI communication is available, it is recommended
to exercise caution while updating registers in the ACTIVE state while the load is being driven. This
is especially important for settings such as S_MODE and S_DIAG which control the critical device
configuration. In order to prevent accidental register writes, the device offers a locking mechanism
through the REG_LOCK bits in the COMMAND register to lock the contents of all configurable
registers. Best practice would be to write all the configurable registers during initialization and then
lock these settings. Run-time register writes for output control are handled by the SPI_IN register,
which offers its own separate locking mechanism through the SPI_IN_LOCK bits.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 53

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

8.6.1 User Registers

The following table lists all the registers that can be accessed by the user. All register addresses NOT listed in this table should be considered as
"reserved" locations and access is blocked to this space. Accessing them will cause a SPI_ERR.
Table 8-26. User Registers

Type (2)

Addr
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DEVICE_ID DEV_ID[5] DEV_ID[4] DEV_ID[3] DEV_ID[2] DEV_ID[1] DEV_ID[0] REV_ID[1] REV_ID[0] R 00h
FAULT_SUMMARY SPI_ERR(3) POR FAULT VMOV VMUV OCP TSD OLA (3) R 01h
STATUS1 OLA1 OLA2 ITRIP_CMP ACTIVE OCP_H1 OCP_L1 OCP_H2 OCP_L2 R 02h
STATUS2 DRVOFF_STAT N/A(4) N/A(4) ACTIVE N/A(4) N/A(4) N/A(4) OLP_CMP R 03h
SPI_IN_LOCK[0]
COMMAND CLR_FLT N/A(4) N/A(4) SPI_IN_LOCK[1] (1) N/A(4) REG_LOCK[1] REG_LOCK[0] (1) R/W 08h

SPI_IN N/A(4) N/A(4) N/A(4) N/A(4) S_DRVOFF (1) S_DRVOFF2 (1) S_EN_IN1 S_PH_IN2 R/W 09h
CONFIG1 EN_OLA VMOV_SEL[1] VMOV_SEL[0] SSC_DIS(1) OCP_RETRY TSD_RETRY VMOV_RETRY OLA_RETRY R/W 0Ah
CONFIG2 PWM_EXTEND S_DIAG[1] S_DIAG[0] N/A(4) N/A(4) S_ITRIP[2] S_ITRIP[1] S_ITRIP[0] R/W 0Bh
CONFIG3 TOFF[1] TOFF[0] (1) N/A(4) S_SR[2] S_SR[1] S_SR[0] S_MODE[1] S_MODE[0] R/W 0Ch
CONFIG4 TOCP_SEL[1] TOCP_SEL[0] N/A(4) OCP_SEL[1] OCP_SEL[0] DRVOFF_SEL(1) EN_IN1_SEL PH_IN2_SEL R/W 0Dh

(1) Defaulted to 1b on reset, others are defaulted to 0b on reset

(2) R = Read Only, R/W = Read/Write
(3) OLA replaced by SPI_ERR in the first SDO byte response, common to all SPI frames. Refer SDO - Standard frame format.
(4) N/A = Not available (read back of this bit will be 0b)

Note
For the pre-production samples, the register map has the following differences:

Table 8-27. Pre-Production Samples - Register Map Differences

Address Name Bit Pre-production samples
02h STATUS1 4 OLP_CMP
03h STATUS2 All Not defined
0Dh CONFIG4 All Not defined

54 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

8.6.1.1 DEVICE_ID register (Address = 00h)

Return to the User Register table.
Device Pre-production samples Final Product
DRV8243S-Q1 30h 32h
DRV8244S-Q1 40h 42h
DRV8245S-Q1 50h 52h
DRV8243P-Q1 Not available 36h
DRV8244P-Q1 Not available 46h
DRV8245P-Q1 Not available 56h

8.6.1.2 FAULT_SUMMARY Register (Address = 01h) [reset = 40h]

Return to the User Register table.
Bit Field Type Reset Description
7 SPI_ERR R 0b 1b indicates that a SPI communication fault has occurred in the previous SPI frame.
6 POR R 1b 1b indicates that a power-on-reset has been detected.
5 FAULT R 0b Logic OR of SPI_ERR, POR, VMOV, VMUV, OCP, TSD & OLA
1b indicates that a VM over voltage has been detected. Refer VMOV_SEL to change
4 VMOV R 0b
thresholds or disable diagnostic, VMOV_RETRY to configure fault reaction.
3 VMUV R 0b 1b indicates that a VM under voltage has been detected.
1b indicates that an over current has been detected in either one or more power FETs. Refer
2 OCP R 0b OCP_SEL, TOCP_SEL to change thresholds & filter times. Refer OCP_RETRY to configure
fault reaction.
1b indicates that an over temperature has been detected. Refer TSD_RETRY to configure
1 TSD R 0b
fault reaction.
1b indicates that an open load condition has been detected in the ACTIVE state. Refer to
0 OLA R 0b
EN_OLA to disable diagnostic, OLA_RETRY to configure fault reaction.

8.6.1.3 STATUS1 Register (Address = 02h) [reset = 00h]

Return to the User Register table.
Bit Field Type Reset Description
7 OLA1 R 0b 1b indicates that an open load condition has been detected in the ACTIVE state on OUT1
6 OLA2 R 0b 1b indicates that an open load condition has been detected in the ACTIVE state on OUT2
5 ITRIP_CMP R 0b 1b indicates that load current has reached the ITRIP regulation level.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 55

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

Bit Field Type Reset Description

4 ACTIVE R 0b 1b indicates that the device is in the ACTIVE state
1b indicates that an over current has been detected on the high-side FET (short to GND) on
3 OCP_H1 R 0b
OUT1
1b indicates that an over current has been detected on the low-side FET (short to VM) on
2 OCP_L1 R 0b
OUT1
1b indicates that an over current has been detected on the high-side FET (short to GND) on
1 OCP_H2 R 0b
OUT2
1b indicates that an over current has been detected on the low-side FET (short to VM) on
0 OCP_L2 R 0b
OUT2

8.6.1.4 STATUS2 Register (Address = 03h) [reset = 80h]

Return to the User Register table.
Bit Field Type Reset Description
7 DRVOFF_STAT R 1b This bit shows the status of the DRVOFF pin. 1b implies the pin status is high.
6, 5 N/A R 0b Not available
4 ACTIVE R 0b 1b indicates that the device is in the ACTIVE state (Copy of bit4 in STATUS1)
3, 2, 1 N/A R 0b Not available
0 OLP_CMP R 0b This bit is the output of the off-state diagnostics (OLP) comparator.

8.6.1.5 COMMAND Register (Address = 08h) [reset = 09h]

Return to the User Register table.
Bit Field Type Reset Description
Clear Fault command - Write 1b to clear all faults reported in the fault registers and de-assert
7 CLR_FLT R/W 0b
the nFAULT pin
6-5 N/A R 0b Not available
Write 10b to unlock the SPI_IN register
4-3 SPI_IN_LOCK R/W 01b Write 01b or 00b or 11b to lock the SPI_IN register
SPI_IN register is locked by default.

2 N/A R 0b Not available

Write 10b to lock the CONFIG registers

1-0 REG_LOCK R/W 01b Write 01b or 00b or 11b to unlock the CONFIG registers
CONFIG registers are unlocked by default.

56 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

8.6.1.6 SPI_IN Register (Address = 09h) [reset = 0Ch]

Return to the User Register table.
Bit Field Type Reset Description
7-4 N/A R 0b Not available
Register bit equivalent of DRVOFF pin when SPI_IN is unlocked. Refer Register Pin control
3 S_DRVOFF R/W 1b
section. In Independent mode, this bit shuts off half-bridge 1.
Register bit to shut off half-bridge 2 in Independent mode when SPI_IN is unlocked. Refer
2 S_DRVOFF2 R/W 1b
Register Pin control section
Register bit equivalent of EN/IN1 pin when SPI_IN is unlocked. Refer Register Pin control
1 S_EN_IN1 R/W 0b
section
Register bit equivalent of PH/IN2 pin when SPI_IN is unlocked. Refer Register Pin control
0 S_PH_IN2 R/W 0b
section

8.6.1.7 CONFIG1 Register (Address = 0Ah) [reset = 10h]

Return to the User Register table.
Bit Field Type Reset Description
Write 1b to enable open load detection in the active state. In Independent mode, OLA is
7 EN_OLA R/W 0b
always disabled for low-side load. Refer DIAG section.
Determines the thresholds for the VM over voltage diagnostics
00b = VM > 35 V

6-5 VMOV_SEL R/W 0b 01b = VM > 28 V

10b = VM > 18 V

11b = VMOV disabled

4 SSC_DIS R/W 1b 0b: Enables the spread spectrum clocking feature

Write 1b to configure fault reaction to retry setting on the detection of over current, else the
3 OCP_RETRY R/W 0b
fault reaction is latched
Write 1b to configure fault reaction to retry setting on the detection of over temperature, else
2 TSD_RETRY R/W 0b
the fault reaction is latched
Write 1b to configure fault reaction to retry setting on the detection of VMOV, else the fault
reaction is latched.

1 VMOV_RETRY R/W 0b Note

For the SPI (P) variant, this bit also controls the fault reaction for a VM under
voltage detection.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 57

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

Bit Field Type Reset Description

Write 1b to configure fault reaction to retry setting on the detection of open load during active,
0 OLA_RETRY R/W 0b
else the fault reaction is latched.

8.6.1.8 CONFIG2 Register (Address = 0Bh) [reset = 00h]

Return to the User Register table.
Bit Field Type Reset Description
Write 1b to access additional Hi-Z (coast) states in the PWM mode - refer PWM EXTEND
7 PWM_EXTEND R/W 0b
table
6-5 S_DIAG R/W 0b Load type indication - refer to DIAG table
4-3 N/A R 0b Not available
2-0 S_ITRIP R/W 0b ITRIP level configuration - refer ITRIP table

8.6.1.9 CONFIG3 Register (Address = 0Ch) [reset = 40h]

Return to the User Register table.
Bit Field Type Reset Description
TOFF time used for ITRIP current regulation
00b = 20 µsec

7-6 TOFF R/W 1b 01b = 30 µsec

10b = 40 µsec

11b = 50 µsec

5 N/A R 0b Not available

4-2 S_SR R/W 0b Slew Rate configuration - refer to Section 8.3.3.1
1-0 S_MODE R/W 0b Device mode configuration - refer MODE table

8.6.1.10 CONFIG4 Register (Address = 0Dh) [reset = 04h]

Return to the User Register table.

58 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

Bit Field Type Reset Description

Filter time for over current detection configuration
00b = 6 µsec

7-6 TOCP_SEL R/W 0b 01b = 3 µsec

10b = 1.5 µsec

11b = Minimum (~0.2 µsec)

5 N/A R 0b Not available

Threshold for over current detection configuration
00b = 100% setting
4-3 OCP_SEL R/W 0b
01b, 11b = 50% setting

10b = 75% setting

DRVOFF pin - register logic combination, when SPI_IN is unlocked

2 DRVOFF_SEL R/W 1b 0b = OR

1b = AND

EN/IN1 pin - register logic combination, when SPI_IN is unlocked

1 EN_IN1_SEL R/W 0b 0b = OR

1b = AND

PH/IN2 pin - register logic combination, when SPI_IN is unlocked

0 PH_IN2_SEL R/W 0b 0b = OR

1b = AND

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 59

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

9.1 Application Information

The DRV824x-Q1 family of devices can be used in a variety of applications that require either a half-bridge
or H-bridge power stage configuration. Common application examples include brushed DC motors, solenoids,
and actuators. The device can also be utilized to drive many common passive loads such as LEDs, resistive
elements, relays, etc. The application examples below will highlight how to use the device in bidirectional current
control applications requiring an H-bridge driver and dual unidirectional current control applications requiring two
half-bridge drivers.
9.1.1 Load Summary
Table 9-1 summarizes the utility of the device features for different type of inductive loads.
Table 9-1. Load Summary Table
Configuration Device Feature
LOAD TYPE Recirculation
Device Slew Rate Current sense ITRIP regulation
Path
Bi-directional motor or DRV824x in PH/EN or PWM
High-side Full range Continuous Useful
solenoid(1) mode
2 Uni-directional motors or Individual load
DRV824x in Independent
low-side solenoids (one side Low-side Limited(4) Discontinuous(3), regulation not
mode (2)
connected to GND) possible
2 High-side solenoids (one DRV824x in Independent
High-side Full range Not available, need external solution
side connected to VM) mode (2)

(1) Solenoid - clamping or quick demagnetization possible, but clamping level will be VM dependent
(2) Independent Hi-Z only supported in the SPI variant
(3) Not sensed during recirculation and during OUTx voltage slew times including tblank
(4) Rising edge slew rate capped at 8 V/µsec for higher settings

VM

nFAULT
IPROPI
Controller I/Os SPI (Opt) DRV824X to Controller ADC
(can be shared) Applicable for
DRVOFF
PWM or
BD

BDC
C

PH/EN solenoid
nSLEEP OUT1
mode
EN/IN1 LOAD
to Controller I/O PH/IN2 OUT2

GND

Figure 9-1. Illustration Showing a Full-Bridge Topology With DRV824X-Q1 in PWM or PH/EN Mode

60 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

VM

nFAULT
to Controller ADC
IPROPI
Controller I/Os SPI (Opt) Summing current Applicable for
(can be shared) DRV824X
DRVOFF

BD
BDC

C
solenoid
Independent
nSLEEP OUT1
mode LOAD
EN/IN1
to Controller I/O PH/IN2 OUT2
LOAD

GND

Figure 9-2. Illustration Showing Half-Bridge Topology to Drive Two Low-side Loads Independently With
DRV824X-Q1 Device in INDEPENDENT Mode

VM VM
nFAULT
HS Switch for
IPROPI to Controller I/O
Controller I/Os SPI (Opt) clamping
Not useful
(can be shared) (OPT)
DRVOFF DRV824X
Independent
mode
nSLEEP OUT1
solenoid
EN/IN1
to Controller I/O PH/IN2 OUT2
solenoid

GND

Figure 9-3. Illustration Showing a Half-Bridge Topology to Drive Two High-side Loads Independently With
DRV824X-Q1 Device in INDEPENDENT Mode

9.2 Typical Application

The figures below show the typical application schematic for driving a brushed DC motor or any inductive load in
various modes. There are several optional connections shown in these schematics, which are listed as follows:
• nSLEEP pin
– SPI (S) variant - This pin can be tied off high in the application if SLEEP function is not needed.
– SPI (P) variant - N/A
– HW (H) variant - Pin control is mandatory even if SLEEP function is not needed. The controller needs to
issue a reset pulse during wake-up to acknowledge wake-up or power-up.
• DRVOFF pin
– Both SPI (P) and SPI (S) variants - This pin can be tied off low in the application if shutoff through pin
function is not needed. The equivalent register bit can be used.
• EN/IN1 pin

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 61

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

– Both SPI (P) and SPI (S) variants - This pin can be tied off low or left floating if register only control is
needed.
• PH/IN2 pin
– Both SPI (P) and SPI (S) variants - This pin can be tied off low or left floating if register only control is
needed.
• IPROPI pin
– All variants - Monitoring of this output is optional. Also IPROPI pin can be tied low if ITRIP feature &
IPROPI function is not needed.
• nFAULT pin
– Both SPI (P) and SPI (S) variants - Monitoring of this output is optional. All diagnostic information can be
read from the STATUS registers.
• SPI input pins
– Both SPI (S) and SPI (P) variants - Inputs (SDI, nSCS, SCLK) are compatible with 3.3 V / 5 V levels.
• SPI SDO pin
– SPI (S) variant - SDO tracks the nSLEEP pin voltage.
– SPI (P) variant - SDO tracks the VDD pin voltage. To interface with a 3.3 V level controller input, a level
shifter or a current limiting series resistor is recommended.
• CONFIG pins
– HW (H) variant - Resistor is not needed for short to GND and Hi-Z level selections
• LVL1 and LVL3 for MODE pin
• LVL1 and LVL6 for SR, ITRIP, DIAG pins
9.2.1 HW Variant

VCC VCC
Reverse Supply
SSOP HW Reverse Supply
Protected Input SSOP HW Protected Input
24 6,7,8,21,22,23 24 6,7,8,21,22,23
I/O nSLEEP VM I/O nSLEEP VM
5 5 CVM2
CVM2 I/O DRVOFF CVM1
I/O DRVOFF CVM1
4 4
I/O EN/IN1 I/O EN/IN1
3 3 18,19,20
CONTROLLER

18,19,20
CONTROLLER

I/O PH/IN2 OUT2 I/O PH/IN2 OUT2 LOAD

25 Oponal (5) 25
Op
onal (5) ADC IPROPI
ADC IPROPI
LOAD

RIPROPI RIPROPI VCC VM / GND

VCC 26
RnFAULT 26 RnFAULT
I/O nFAULT I/O nFAULT
27 27 9,10,11
MODE 9,10,11 MODE OUT1 LOAD
RMODE OUT1 RMODE
2 2
DIAG DIAG
Op onal (7)
Op onal (7)

RDIAG 12,13,14, RDIAG 12,13,14,

28 28
15,16,17 15,16,17
ITRIP GND  ITRIP GND
RITRIP RITRIP
1 1
SR SR
RSR RSR

FB with PH/EN or PWM mode HS/ LS load in Independent mode

Figure 9-4. Typical Application Schematic - HW Variant in HVSSOP Package

62 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

VCC VCC

VQFN-HR HW VQFN-HR HW Reverse Supply

Reverse Supply
3 4 3 4 Protected Input
Protected Input I/O nSLEEP
I/O nSLEEP VM VM
8 8 CVM2
CVM2 I/O DRVOFF CVM1
I/O DRVOFF CVM1
9 9
I/O EN/IN1 I/O EN/IN1
10 5 10 5

CONTROLLER
CONTROLLER

I/O PH/IN2 OUT2 I/O PH/IN2 OUT2 LOAD

Op
onal (5) 2 Oponal (5) 2
ADC IPROPI ADC IPROPI

LOAD
RIPROPI ) RIPROPI VCC VM / GND
VCC 1
RnFAULT 1 RnFAULT
I/O nFAULT I/O nFAULT
14 7 14 7
MODE OUT1 MODE OUT1 LOAD
RMODE RMODE
11 11
DIAG DIAG

Op onal (7)
Op onal (7)

RDIAG RDIAG
13 6 13 6
ITRIP GND  ITRIP GND
RITRIP RITRIP
12 12
SR SR
RSR RSR

FB with PH/EN or PWM mode HS/ LS load in Independent mode

Figure 9-5. Typical Application Schematic - HW Variant in VQFN-HR Package

9.2.2 SPI Variant

VCC VCC
Reverse Supply
Reverse Supply
Protected Input
SSOP SPI Protected Input SSOP SPI
24 Oponal (1) 24 6,7,8,21,22,23
Op
onal (1) 6,7,8,21,22,23
I/O nSLEEP
I/O nSLEEP VM VM
5 Oponal (2) 5 CVM2
Op onal (2) CVM2 I/O DRVOFF CVM1
I/O DRVOFF CVM1
Oponal (3) 4 Oponal (3) 4
I/O EN/IN1 I/O EN/IN1

Oponal (4) 3 Op onal (4) 3 18,19,20

CONTROLLER

18,19,20
CONTROLLER

I/O PH/IN2 OUT2 I/O PH/IN2 OUT2 LOAD

Oponal (5) 25 Op
onal (5) 25
ADC IPROPI ADC IPROPI
LOAD

RIPROPI RIPROPI VCC VM / GND

VCC 26
RnFAULT 26 RnFAULT
I/O nFAULT I/O nFAULT
Oponal (6) Oponal (6)
27 27 9,10,11
9,10,11 SDO OUT1 LOAD
SDO OUT1
Daisy Chain capable
Daisy Chain capable

2 2
S nSCS S nSCS
12,13,14, 12,13,14,
P 28 15,16,17 P 28
SDI GND 15,16,17
SDI GND
I 1 I 1
SCLK SCLK

FB with PH/EN or PWM mode HS/ LS load in Independent mode

Figure 9-6. Typical Application Schematic - SPI (S) Variant in HVSSOP Package

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 63

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

VCC VCC
Reverse Supply
Reverse Supply
Protected Input
SSOP SPI Protected Input SSOP SPI
24 6,7,8,21,22,23 24 6,7,8,21,22,23
Logic Supply Logic Supply VDD VM
VDD VM
5 Oponal (2) 5 CVM2
Op
onal (2) CVM2 I/O DRVOFF CVM1
I/O DRVOFF CVM1
Op onal (3) 4 Oponal (3) 4
I/O EN/IN1 I/O EN/IN1

Oponal (4) 3 Oponal (4) 3 18,19,20

CONTROLLER
18,19,20
CONTROLLER

I/O PH/IN2 OUT2 I/O PH/IN2 OUT2 LOAD

Oponal (5) 25 Oponal (5) 25
ADC IPROPI ADC IPROPI

LOAD
RIPROPI RIPROPI VCC VM / GND
VCC 26
RnFAULT 26 RnFAULT
I/O nFAULT I/O nFAULT
Oponal (6) Op onal (6)
27 27 9,10,11
9,10,11 SDO OUT1 LOAD
SDO OUT1

Daisy Chain capable

Daisy Chain capable

2 2
S nSCS S nSCS
12,13,14, 12,13,14,
P 28 15,16,17 P 28
SDI GND 15,16,17
SDI GND
I 1 I 1
SCLK SCLK

FB with PH/EN or PWM mode HS/ LS load in Independent mode

Figure 9-7. Typical Application Schematic - SPI (P) Variant in HVSSOP Package

VCC VCC

VQFN-HR SPI Reverse Supply

VQFN-HR SPI Reverse Supply
3 Oponal (1) 3 4
Op
onal (1) 4 Protected Input I/O nSLEEP
Protected Input
I/O nSLEEP VM VM
8 Oponal (2) 8 CVM2
Op onal (2) CVM2 I/O DRVOFF CVM1
I/O DRVOFF CVM1
Oponal (3) 9 Oponal (3) 9
I/O EN/IN1 I/O EN/IN1
5 Op onal (4) 10 5
Oponal (4) 10
CONTROLLER
CONTROLLER

I/O PH/IN2 OUT2 I/O PH/IN2 OUT2 LOAD

Oponal (5) 2 Op
onal (5) 2
ADC IPROPI ADC IPROPI
LOAD

RIPROPI RIPROPI VCC VM / GND

VCC 1
RnFAULT 1 RnFAULT
I/O nFAULT I/O nFAULT
Oponal (6) Oponal (6)
14 7 14 7
SDO OUT1 SDO OUT1 LOAD
Daisy Chain capable
Daisy Chain capable

11 11
S nSCS S nSCS

P 13 6 P 13
SDI GND
6
SDI GND
I 12 I 12
SCLK SCLK

FB with PH/EN or PWM mode HS/ LS load in Independent mode

Figure 9-8. Typical Application Schematic - SPI (S) Variant in VQFN-HR Package

64 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

10 Power Supply Recommendations

The device is designed to operate with an input voltage supply (VM) range from 4.5 V to 40 V. A 0.1-µF ceramic
capacitor rated for VM must be placed as close to the device as possible. Also, an appropriately sized bulk
capacitor must be placed on the VM pin.
10.1 Bulk Capacitance Sizing
Bulk capacitance sizing is an important factor in motor drive system design. It is beneficial to have more bulk
capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors including:
• The highest current required by the motor system.
• The capacitance of the power supply and the ability of the power supply to source current.
• The amount of parasitic inductance between the power supply and motor system.
• The acceptable voltage ripple.
• The type of motor used (brushed DC, brushless DC, and stepper).
• The motor braking method.
The inductance between the power supply and motor drive system limits the rate that current can change from
the power supply. If the local bulk capacitance is too small, the system responds to excessive current demands
or dumps from the motor with a change in voltage. When sufficient bulk capacitance is used, the motor voltage
remains stable, and high current can be quickly supplied.
The data sheet provides a recommended value, but system-level testing is required to determine the appropriate
sized bulk capacitor.

Parasitic Wire
Inductance
Power Supply Motor Drive System

VM

+ +
Motor Driver
±

GND

Local IC Bypass
Bulk Capacitor Capacitor

Figure 10-1. Example Setup of Motor Drive System With External Power Supply

The voltage rating for bulk capacitors should be higher than the operating voltage to provide a margin for cases
when the motor transfers energy to the supply.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 65

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

11 Layout
11.1 Layout Guidelines
Each VM pin must be bypassed to ground using low-ESR ceramic bypass capacitors with recommended values
of 0.1 μF rated for VM. These capacitors should be placed as close to the VM pins as possible with a thick trace
or ground plane connection to the device GND pin.
Additional bulk capacitance is required to bypass the high current path. This bulk capacitance should be placed
such that it minimizes the length of any high current paths. The connecting metal traces should be as wide as
possible, with numerous vias connecting PCB layers. These practices minimize inductance and allow the bulk
capacitor to deliver high current.
For the SPI (P) device variant, VDD pin may be bypassed to ground using low-ESR ceramic 6.3 V bypass
capacitor with recommended values of 0.1 μF.
11.2 Layout Example
The following figure shows a layout example for a 4 cm X 4 cm x 1.6 mm, 4 layer PCB for a leaded package
device. The 4 layers uses 2 oz copper on top/ bottom signal layers and 1 oz copper on internal supply layers,
with 0.3 mm thermal via drill diameter, 0.025 mm Cu plating, 1 mm minimum via pitch. The same layout can be
adopted for the non-leaded VQFN-HR package as well. The Section 7.5.14 for the 4 cm X 4 cm X 1.6 mm is
based on a similar layout.
Note: The layout example shown is for a full bridge topology using DRV824xQ1 device in SSOP package.

Figure 11-1. Layout example: 4cm x 4 cm x 1.6mm, 4 layer PCB

66 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

12 Device and Documentation Support

12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, Full Bridge Driver Junction Temperature Estimator (Excel-based worksheet)
• Texas Instruments, Calculating Motor Driver Power Dissipation application report
• Texas Instruments, Current Recirculation and Decay Modes application report
• Texas Instruments, PowerPAD™ Made Easy application report
• Texas Instruments, PowerPAD™ Thermally Enhanced Package application report
• Texas Instruments, Understanding Motor Driver Current Ratings application report
• Texas Instruments, Best Practices for Board Layout of Motor Drivers application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.3 Community Resources
12.4 Trademarks
All trademarks are the property of their respective owners.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and order-able information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 67

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

68 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 69

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

Figure 13-1. DGQ28A: HVSSOP(28) Package Drawing

70 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 DRV8243-Q1
www.ti.com SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022

13.1 Tape and Reel Information

REEL DIMENSIONS TAPE DIMENSIONS
K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants
Reel Reel
Package Package A0 B0 K0 P1 W Pin1
Device Pins SPQ Diameter Width W1
Type Drawing (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) (mm)
PDRV8243SDGQQ1 HVSSOP DGQ 28 3000 330 16.4 5.50 7.40 1.45 8.00 16.00 Q1
PDRV8243PDGQQ1 HVSSOP DGQ 28 3000 330 16.4 5.50 7.40 1.45 8.00 16.00 Q1
PDRV8243HDGQQ1 HVSSOP DGQ 28 3000 330 16.4 5.50 7.40 1.45 8.00 16.00 Q1
PDRV8243SRXYQ1 VQFN-HR RXY 14 5000 180 12.4 2.45 2.75 1.2 4 12 Q1

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 71

Product Folder Links: DRV8243-Q1
DRV8243-Q1
SLVSG23A – DECEMBER 2021 – REVISED JANUARY 2022 www.ti.com

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

L
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
PDRV8243SDGQQ1 HVSSOP DGQ 28 3000 356 356 35
PDRV8243PDGQQ1 HVSSOP DGQ 28 3000 356 356 35
PDRV8243HDGQQ1 HVSSOP DGQ 28 3000 356 356 35
PDRV8243SRXYQ1 VQFN-HR RXY 14 5000 210 185 35

72 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: DRV8243-Q1

 PACKAGE OPTION ADDENDUM

www.ti.com 6-Dec-2021

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

PDRV8243HRXYQ1 ACTIVE VQFN-HR RXY 14 5000 TBD Call TI Call TI -40 to 125

PDRV8243SDGQQ1 ACTIVE HVSSOP DGQ 28 1 TBD Call TI Call TI -40 to 125

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Dec-2021

Addendum-Page 2
 PACKAGE OUTLINE
RXY0014A VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
A
3.1
B 2.9

PIN 1 INDEX AREA 0.100 MIN

4.6
4.4

(0.130)

SECTION A-A
TYPICAL

1 MAX C

.05 0.08 C
.00 2X 3.1
2.9
2X 1.475
1.275
1.2 (0.15) TYP (0.2) TYP
1.0
6X (0.4) TYP

1.35 6

(0.16)
10X 0.3
0.2
0.65 7
0.1 C A B
0.05 C
PKG 0
0.05

0.625

1.125 10X 0.3

0.2
0.1 C A B
1.625 10
1 0.05 C

PIN1 ID 14 11
(OPTIONAL) 10X 0.5
0.3
PKG 0
0.75

0.25

4226096/A 08/2020
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

www.ti.com
 EXAMPLE BOARD LAYOUT
RXY0014A VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

(0.9125)

(0.9125)
(0) PKG
(0.75)

(0.25)

(0.25)

(0.75)
(1.4)

(1.4)
14 11
10X (0.6)
(2.15)

(1.625) 1
10
(R0.05) TYP
10X (0.25)
(1.125)

(0.625) 6X (0.4) TYP

(0.05)
PKG (0)
6X (0.25)

(0.65) 7

(0.35) TYP

(1.35) 6

(1.8) (1.3)

SOLDER MASK
OPENING
METAL UNDER 4X
SOLDER MASK 2X (1.575) (0.25)

2X (3.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 18X

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND METAL UNDER
METAL
SOLDER MASK

EXPOSED SOLDER MASK EXPOSED SOLDER MASK

METAL OPENING METAL OPENING

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS 4226096/A 08/2020

NOTES: (continued)

3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) .
4. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
RXY0014A VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

(0) PKG
(0.9125)

(0.9125)
(0.75)

(0.25)

(0.25)

(0.75)
(1.4)

(0.9)

(0.9)

(1.4)
4X (1.6)
14 11
10X (0.6)
(2.15)

(1.625) 1
10
(R0.05) TYP
10X (0.25)
(1.125)

(0.2)
(0.625) 6X (0.4) TYP
TYP

(0.05)
PKG (0)
6X (0.25)

(0.65) 7

(0.35) TYP

(1.35) 6

(0.2)
4X (0.7)
(2.1)

METAL UNDER 4X
SOLDER MASK (0.25)
2X (1.575)

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE: 18X

4226096/A 08/2020

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated