DRV8350F, DRV8353F

SLVSFV1B – AUGUST 2018 – REVISED AUGUST 2021

DRV835xF 100-V Three-Phase Smart Gate Driver

components that are typically necessary for MOSFET
1 Features slew rate control and protection circuits. The
• 9 to 100-V, Triple half-bridge gate driver SGD architecture also optimizes dead time to
– Optional triple low-side current shunt amplifiers prevent shoot-through conditions, provides flexibility
• Functional Safety Quality-Managed in decreasing electromagnetic interference (EMI) by
– Documentation available to aid IEC 61800-5-2 MOSFET slew rate control, and protects against gate
functional safety system design short circuit conditions through VGS monitors. A strong
• Smart gate drive architecture gate pulldown circuit helps prevent unwanted dV/dt
– Adjustable slew rate control for EMI parasitic gate turn on events
performance Various PWM control modes (6x, 3x, 1x, and
– VGS handshake and minimum dead-time independent) are supported for simple interfacing to
insertion to prevent shoot-through the external controller. These modes can decrease
– 50-mA to 1-A peak source current the number of outputs required of the controller for
– 100-mA to 2-A peak sink current the motor driver PWM control signals. This family
– dV/dt mitigation through strong pulldown of devices also includes 1x PWM mode for simple
• Integrated gate driver power supplies sensored trapezoidal control of a BLDC motor by
– High-side doubler charge pump For 100% using an internal block commutation table.
PWM duty cycle control
Device Information
– Low-side linear regulator (1)PART NUMBER PACKAGE BODY SIZE (NOM)
• Integrated triple current shunt amplifiers
DRV8350F WQFN (32) 5.00 mm × 5.00 mm
– Adjustable gain (5, 10, 20, 40 V/V)
– Bidirectional or unidirectional support DRV8353F WQFN (40) 6.00 mm × 6.00 mm
• 6x, 3x, 1x, and independent PWM modes (1) For all available packages, see the orderable addendum at
– Supports 120° sensored operation the end of the data sheet.
• SPI or hardware interface available 9 to 75 V 7 to 100 V
• Low-power sleep mode (20 µA at VVM = 48-V)
• Integrated protection features DRV835xF Drain
Sense
PWM
– VM undervoltage lockout (UVLO)

N-Channel
MOSFETs
Three-Phase
SPI or H/W M
– Gate drive supply undervoltage (GDUV)
Controller

Smart Gate Driver Gate Drive

– MOSFET VDS overcurrent protection (OCP) nFAULT

Current
– MOSFET shoot-through prevention Current Sense
3x Shunt Amplifiers
Sense

– Gate driver fault (GDF) Protection

– Thermal warning and shutdown (OTW/OTSD)
– Fault condition indicator (nFAULT)
Simplified Schematic
2 Applications
• 3-phase brushless-DC (BLDC) motor modules
• Servo drives, Factory automation
• Linear motor transport systems
• Industrial collaborative robot
• Autonomous Guided Vehicle, Delivery Drones
• E-Bikes, E-scooters, and E-mobility
3 Description
The DRV835xF family of devices are highly-integrated
gate drivers for three-phase brushless DC (BLDC)
motor applications. The device variants provide
optional integrated current shunt amplifiers to support
different motor control schemes.
The DRV835xF uses smart gate drive (SGD)
architecture to decrease the number of external

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 8.5 Programming............................................................ 45
2 Applications..................................................................... 1 8.6 Register Maps...........................................................47
3 Description.......................................................................1 9 Application and Implementation.................................. 56
4 Revision History.............................................................. 2 9.1 Application Information............................................. 56
5 Device Comparison Table...............................................3 9.2 Typical Application.................................................... 56
6 Pin Configuration and Functions...................................3 10 Power Supply Recommendations..............................68
Pin Functions—32-Pin DRV8350F Devices......................3 10.1 Bulk Capacitance Sizing......................................... 68
Pin Functions—40-Pin DRV8353F Devices......................4 11 Layout........................................................................... 69
7 Specifications.................................................................. 6 11.1 Layout Guidelines................................................... 69
7.1 Absolute Maximum Ratings........................................ 6 11.2 Layout Example...................................................... 70
7.2 ESD Ratings............................................................... 6 12 Device and Documentation Support..........................71
7.3 Recommended Operating Conditions.........................7 12.1 Device Support....................................................... 71
7.4 Thermal Information....................................................7 12.2 Documentation Support.......................................... 71
7.5 Electrical Characteristics.............................................8 12.3 Related Links.......................................................... 72
7.6 SPI Timing Requirements......................................... 14 12.4 Receiving Notification of Documentation Updates..72
7.7 Typical Characteristics.............................................. 15 12.5 Support Resources................................................. 72
8 Detailed Description......................................................17 12.6 Trademarks............................................................. 72
8.1 Overview................................................................... 17 12.7 Electrostatic Discharge Caution..............................72
8.2 Functional Block Diagram......................................... 18 12.8 Glossary..................................................................72
8.3 Feature Description...................................................21 13 Mechanical, Packaging, and Orderable
8.4 Device Functional Modes..........................................44 Information.................................................................... 72

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (October 2020) to Revision B (August 2021) Page

• Removed references to DRV8353RF and DRV8350RF.....................................................................................1
• Updated Primary and Alternative Application Diagrams...................................................................................56
• Updated Layout Example................................................................................................................................. 70
• Updated Device Nomenclature.........................................................................................................................71

Changes from Revision * (August 2018) to Revision A (October 2020) Page

• Changed document status to production data.................................................................................................... 1
• Deleted preview only note from DRV8350 and DRV8353 devices..................................................................... 1

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5 Device Comparison Table

DEVICE VARIANT SHUNT AMPLIFIERS INTERFACE
DRV8350FH Hardware (H)
DRV8350F 0
DRV8350FS SPI (S)
DRV8353FH Hardware (H)
DRV8353F 3
DRV8353FS SPI (S)

6 Pin Configuration and Functions

DVDD

DVDD
VGLS

VGLS
INHC

INHC
INHB

INHB
INLC

INLC
GND

INLB

GND

INLB
CPL

CPL
32

31

30

29

28

27

26

25

32

31

30

29

28

27

26

25
CPH 1 24 INLA CPH 1 24 INLA

VM 2 23 INHA VM 2 23 INHA

VDRAIN 3 22 ENABLE VDRAIN 3 22 ENABLE

VCP 4 21 NC VCP 4 21 nSCS

Thermal Thermal
GHA 5 Pad 20 VDS GHA 5 Pad 20 SCLK

SHA 6 19 IDRIVE SHA 6 19 SDI

GLA 7 18 MODE GLA 7 18 SDO

SLA 8 17 nFAULT SLA 8 17 nFAULT

10

11

12

13

14

15

16

10

11

12

13

14

15

16
9

9
SLB

GLB

SHB

GHB

GHC

SHC

GLC

SLC

SLB

GLB

SHB

GHB

GHC

SHC

GLC

SLC
Not to scale Not to scale

Figure 6-1. DRV8350FH RTV Package 32-Pin WQFN Figure 6-2. DRV8350FS RTV Package 32-Pin WQFN
With Exposed Thermal Pad Top View With Exposed Thermal Pad Top View

Pin Functions—32-Pin DRV8350F Devices

PIN
NO. TYPE(1) DESCRIPTION
NAME
DRV8350FH DRV8350FS
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
CPH 1 1 PWR
pins.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
CPL 32 32 PWR
pins.
5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This
DVDD 29 29 PWR
regulator can source up to 10 mA externally.
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs pulse can be used
ENABLE 22 22 I
to reset fault conditions.
GHA 5 5 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 12 12 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 13 13 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 7 7 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 10 10 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 15 15 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GND 30 30 PWR Device primary ground. Connect to system ground.
IDRIVE 19 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA 23 23 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 25 25 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 27 27 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 24 24 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.

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PIN
NO. TYPE(1) DESCRIPTION
NAME
DRV8350FH DRV8350FS
INLB 26 26 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 28 28 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE 18 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
NC 21 — NC No internal connection. This pin can be left floating or connected to system ground.
nFAULT 17 17 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS — 21 I Serial chip select. A logic low on this pin enables serial interface communication.
SCLK — 20 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI — 19 I Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO — 18 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA 6 6 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 11 11 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 14 14 I High-side source sense input. Connect to the high-side power MOSFET source.
SLA 8 8 I Low-side source sense input. Connect to the low-side power MOSFET source.
SLB 9 9 I Low-side source sense input. Connect to the low-side power MOSFET source.
SLC 16 16 I Low-side source sense input. Connect to the low-side power MOSFET source.
VCP 4 4 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
VDRAIN 3 3 I High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS 20 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VGLS 31 31 PWR 11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R,
VM 2 2 PWR
0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.

(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain

ENABLE

ENABLE
DVDD

DVDD
VGLS

VGLS
INHC

INHC
INHB

INHA

INHB

INHA
INLC

INLC
GND

INLB

INLA

GND

INLB

INLA
40

39

38

37

36

35

34

33

32

31

40

39

38

37

36

35

34

33

32

31
CPL 1 30 GAIN CPL 1 30 nSCS

CPH 2 29 VDS CPH 2 29 SCLK

VM 3 28 IDRIVE VM 3 28 SDI

VDRAIN 4 27 MODE VDRAIN 4 27 SDO

VCP 5 26 nFAULT VCP 5 26 nFAULT

Thermal Thermal
GHA 6 Pad 25 AGND GHA 6 Pad 25 AGND

SHA 7 24 VREF SHA 7 24 VREF

GLA 8 23 SOA GLA 8 23 SOA

SPA 9 22 SOB SPA 9 22 SOB

SNA 10 21 SOC SNA 10 21 SOC

11

12

13

14

15

16

17

18

19

20

11

12

13

14

15

16

17

18

19

20
SNB

SPB

GLB

SHB

GHB

GHC

SHC

GLC

SPC

SNC

SNB

SPB

GLB

SHB

GHB

GHC

SHC

GLC

SPC

SNC

Not to scale Not to scale

Figure 6-3. DRV8353FH RTA Package 40-Pin WQFN Figure 6-4. DRV8353FS RTA Package 40-Pin WQFN
With Exposed Thermal Pad Top View With Exposed Thermal Pad Top View

Pin Functions—40-Pin DRV8353F Devices

PIN
NO. TYPE(1) DESCRIPTION
NAME
DRV8353FH DRV8353FS
AGND 25 25 PWR Device analog ground. Connect to system ground.
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
CPH 2 2 PWR
pins.

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PIN
NO. TYPE(1) DESCRIPTION
NAME
DRV8353FH DRV8353FS
Charge pump switching node. Connect a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor between the CPH and CPL
CPL 1 1 PWR
pins.
5-V internal regulator output. Connect a X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the DVDD and GND pins. This
DVDD 38 38 PWR
regulator can source up to 10 mA externally.
Gate driver enable. When this pin is logic low the device goes to a low power sleep mode. An 8 to 40-µs low pulse can be
ENABLE 31 31 I
used to reset fault conditions.
GAIN 30 — I Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GND 39 39 PWR Device power ground. Connect to system ground.
GHA 6 6 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHB 15 15 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GHC 16 16 O High-side gate driver output. Connect to the gate of the high-side power MOSFET.
GLA 8 8 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLB 13 13 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
GLC 18 18 O Low-side gate driver output. Connect to the gate of the low-side power MOSFET.
IDRIVE 28 — I Gate drive output current setting. This pin is a 7 level input pin set by an external resistor.
INHA 32 32 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHB 34 34 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INHC 36 36 I High-side gate driver control input. This pin controls the output of the high-side gate driver.
INLA 33 33 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLB 35 35 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
INLC 37 37 I Low-side gate driver control input. This pin controls the output of the low-side gate driver.
MODE 27 — I PWM input mode setting. This pin is a 4 level input pin set by an external resistor.
nFAULT 26 26 OD Fault indicator output. This pin is pulled logic low during a fault condition and requires an external pullup resistor.
nSCS — 30 I Serial chip select. A logic low on this pin enables serial interface communication.
SCLK — 29 I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin.
SDI — 28 I Serial data input. Data is captured on the falling edge of the SCLK pin.
SDO — 27 OD Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor.
SHA 7 7 I High-side source sense input. Connect to the high-side power MOSFET source.
SHB 14 14 I High-side source sense input. Connect to the high-side power MOSFET source.
SHC 17 17 I High-side source sense input. Connect to the high-side power MOSFET source.
SNA 10 10 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNB 11 11 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SNC 20 20 I Shunt amplifier input. Connect to the low-side of the current shunt resistor.
SOA 23 23 O Shunt amplifier output.
SOB 22 22 O Shunt amplifier output.
SOC 21 21 O Shunt amplifier output.
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current
SPA 9 9 I
shunt resistor.
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current
SPB 12 12 I
shunt resistor.
Low-side source sense and shunt amplifier input. Connect to the low-side power MOSFET source and high-side of the current
SPC 19 19 I
shunt resistor.
VCP 5 5 PWR Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VCP and VDRAIN pins.
VDRAIN 4 4 I High-side MOSFET drain sense input and charge pump reference. Connect to the common point of the MOSFET drains.
VDS 29 — I VDS monitor trip point setting. This pin is a 7 level input pin set by an external resistor.
VGLS 40 40 PWR 11-V internal regulator output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VGLS and GND pins.
Gate driver power supply input. Connect to either VDRAIN or separate gate driver supply voltage. Connect a X5R or X7R,
VM 3 3 PWR
0.1-µF, VM-rated ceramic and greater then or equal to 10-uF local capacitance between the VM and GND pins.
Shunt amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF
VREF 24 24 PWR
and AGND pins.

(1) PWR = power, I = input, O = output, NC = no connection, OD = open-drain

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7 Specifications
7.1 Absolute Maximum Ratings
at TA = –40°C to +125°C (unless otherwise noted)(1)
MIN MAX UNIT
GATE DRIVER
Power supply pin voltage (VM) –0.3 80 V
Voltage differential between ground pins (AGND, BGND, DGND, PGND) –0.3 0.3 V
MOSFET drain sense pin voltage (VDRAIN) –0.3 102 V
MOSFET drain sense pin voltage slew rate (VDRAIN) 0 2 V/µs
Charge pump pin voltage (CPH, VCP) –0.3 VVDRAIN + 16 V
Charge-pump negative-switching pin voltage (CPL) –0.3 VVDRAIN V
Low-side gate drive regulator pin voltage (VGLS) –0.3 18 V
Internal logic regulator pin voltage (DVDD) –0.3 5.75 V
Digital pin voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nFAULT, nSCS, SCLK, SDI, SDO,
–0.3 5.75 V
VDS)
Continuous high-side gate drive pin voltage (GHx) –5(2) VVCP + 0.3 V
Transient 200-ns high-side gate drive pin voltage (GHx) –10 VVCP + 0.3 V
High-side gate drive pin voltage with respect to SHx (GHx) –0.3 16 V
Continuous high-side source sense pin voltage (SHx) –5(2) 102 V
Continuous high-side source sense pin voltage (SHx) –5(2) VVDRAIN + 5 V
Transient 200-ns high-side source sense pin voltage (SHx) –10 VVDRAIN + 10 V
Continuous low-side gate drive pin voltage (GLx) –1.0 VVGLS + 0.3 V
Transient 200-ns low-side gate drive pin voltage (GLx) –5.0 VVGLS + 0.3 V
Gate drive pin source current (GHx, GLx) Internally limited Internally limited A
Gate drive pin sink current (GHx, GLx) Internally limited Internally limited A
Continuous low-side source sense pin voltage (SLx) –1 1 V
Transient 200-ns low-side source sense pin voltage (SLx) –5 5 V
Continuous shunt amplifier input pin voltage (SNx, SPx) –1 1 V
Transient 200-ns shunt amplifier input pin voltage (SNx, SPx) –5 5 V
Reference input pin voltage (VREF) –0.3 5.75 V
Shunt amplifier output pin voltage (SOx) –0.3 VVREF + 0.3 V
Ambient temperature, TA –40 125 °C
Junction temperature, TJ –40 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) VDRAIN pin voltage with respect to high-side gate pin (GHx) and phase node pin voltage (SHx) should be limited to 102 V maximum.
This will limit the GHx and SHx pin negative voltage capability when VDRAIN is greater than 92 V.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as
±2000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500
V may actually have higher performance.

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7.3 Recommended Operating Conditions

at TA = –40°C to +125°C (unless otherwise noted)
MIN MAX UNIT
GATE DRIVER
VVM Gate driver power supply voltage (VM) 9 75 V
VVDRAIN Charge pump reference and drain voltage sense (VDRAIN) 7 100 V
VI Input voltage (ENABLE, GAIN, IDRIVE, INHx, INLx, MODE, nSCS, SCLK, SDI, VDS) 0 5.5 V
fPWM Applied PWM signal (INHx, INLx) 0 200(1) kHz
tSH Switch-node slew rate range (SHx) 0 2 V/ns
IGATE_HS High-side average gate-drive current (GHx) 0 25(1) mA
IGATE_LS Low-side average gate-drive current (GLx) 0 25(1) mA
IDVDD External load current (DVDD) 0 10(1) mA
VVREF Reference voltage input (VREF) 3 5.5 V
ISO Shunt amplifier output current (SOx) 0 5 mA
VOD Open drain pullup voltage (nFAULT, SDO) 0 5.5 V
IOD Open drain output current (nFAULT, SDO) 0 5 mA
TA Operating ambient temperature –40 125 °C
TJ Operating junction temperature –40 150 °C

(1) Power dissipation and thermal limits must be observed.

7.4 Thermal Information

DRV8350F DRV8353F
THERMAL METRIC(1) RTV (WQFN) RTA (WQFN) UNIT
32 PINS 40 PINS
RθJA Junction-to-ambient thermal resistance 29.2 26.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 15.2 13.1 °C/W
RθJB Junction-to-board thermal resistance 9.2 8.4 °C/W
ψJT Junction-to-top characterization parameter 0.1 0.1 °C/W
ψJB Junction-to-board characterization parameter 9.2 8.4 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.2 1.1 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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7.5 Electrical Characteristics

at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES (DVDD, VCP, VGLS, VM)
IVM VM operating supply current VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V 8.5 13 mA
IVDRAIN VDRAIN operating supply current VVM = VVDRAIN = 48 V, ENABLE = 3.3 V, INHx/INLx = 0 V 1.9 4 mA
ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 25°C 20 40
ISLEEP Sleep mode supply current µA
ENABLE = 0 V, VVM = VVDRAIN = 48 V, TA = 125°C 100
tRST Reset pulse time ENABLE = 0 V period to reset faults 5 40 µs
tWAKE Turnon time VVM > VUVLO, ENABLE = 3.3 V to outputs ready 1 ms
tSLEEP Turnoff time ENABLE = 0 V to device sleep mode 1 ms
VDVDD DVDD regulator voltage IDVDD = 0 to 10 mA 4.75 5 5.25 V
VVM = 15 V, IVCP = 0 to 25 mA 9 10.5 12

VCP operating voltage VVM = 12 V, IVCP = 0 to 20 mA 7.5 10 11.5

VVCP V
with respect to VDRAIN VVM = 10 V, IVCP = 0 to 15 mA 6 8 9.5
VVM = 9 V, IVCP = 0 to 10 mA 5.5 7.5 8.5

VGLS operating voltage VVM = 15 V, IVGLS = 0 to 25 mA 13 14.5 16

VVGLS V
with respect to GND VVM = 12 V, IVGLS = 0 to 20 mA 10 11.5 12.5

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at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VVM = 10 V, IVGLS = 0 to 15 mA 8 9.5 10.5
VVM = 9 V, IVGLS = 0 to 10 mA 7 8.5 9.5
LOGIC-LEVEL INPUTS (ENABLE, INHx, INLx, nSCS, SCLK, SDI)
VIL Input logic low voltage 0 0.8 V
VIH Input logic high voltage 1.5 5.5 V
VHYS Input logic hysteresis 100 mV
IIL Input logic low current VVIN = 0 V –5 5 µA
IIH Input logic high current VVIN = 5 V 50 70 µA
RPD Pulldown resistance To GND 100 kΩ
tPD Propagation delay INHx/INLx transition to GHx/GLx transition 200 ns
FOUR-LEVEL H/W INPUTS (GAIN, MODE)
VI1 Input mode 1 voltage Tied to GND 0 V
VCOMP1 Quad-level voltage comparator 1 Voltage comparator between VI1 and VI2 1.156 1.256 1.356 V
VI2 Input mode 2 voltage 47 kΩ ± 5% to tied GND 1.9 V
VCOMP2 Quad-level voltage comparator 1 Voltage comparator between VI2 and VI3 2.408 2.508 2.608 V
VI3 Input mode 3 voltage Hi-Z 3.1 V
VCOMP3 Quad-level voltage comparator 3 Voltage comparator between VI3 and VI4 3.614 3.714 3.814 V
VI4 Input mode 4 voltage Tied to DVDD 5 V
RPU Pullup resistance Internal pullup to DVDD 50 kΩ
RPD Pulldown resistance Internal pulldown to GND 84 kΩ
SEVEN-LEVEL H/W INPUTS (IDRIVE, VDS)
VI1 Input mode 1 voltage Tied to GND 0 V
VCOMP1 Seven-level voltage comparator 1 Voltage comparator between VI1 and VI2 0.057 0.157 0.257 V
VI2 Input mode 2 voltage 18 kΩ ± 5% tied to GND 0.8 V
VCOMP2 Seven-level voltage comparator 2 Voltage comparator between VI2 and VI3 1.158 1.258 1.358 V
VI3 Input mode 3 voltage 75 kΩ ± 5% tied to GND 1.7 V
VCOMP3 Seven-level voltage comparator 3 Voltage comparator between VI3 and VI4 2.257 2.357 2.457 V
VI4 Input mode 4 voltage Hi-Z 2.5 V
VCOMP4 Seven-level voltage comparator 4 Voltage comparator between VI4 and VI5 2.561 2.661 2.761 V
VI5 Input mode 5 voltage 75 kΩ ± 5% tied to DVDD 3.3 V
VCOMP5 Seven-level voltage comparator 5 Voltage comparator between VI5 and VI6 3.615 3.715 3.815 V
VI6 Input mode 6 voltage 18 kΩ ± 5% tied to DVDD 4.2 V
VCOMP6 Seven-level voltage comparator 6 Voltage comparator between VI6 and VI7 4.75 4.85 4.95 V
VI7 Input mode 7 voltage Tied to DVDD 5 V
RPU Pullup resistance Internal pullup to DVDD 73 kΩ
RPD Pulldown resistance Internal pulldown to GND 73 kΩ
OPEN DRAIN OUTPUTS (nFAULT, SDO)
VOL Output logic low voltage IO = 5 mA 0.125 V
IOZ Output high impedance leakage VO = 5 V –2 2 µA
GATE DRIVERS (GHx, GLx)
VVM = 15 V, IVCP = 0 to 25 mA 9 10.5 12

High-side gate drive voltage VVM = 12 , IVCP = 0 to 20 mA 7.5 10 11.5

VGSH V
with respect to SHx VVM = 10 V, IVCP = 0 to 15 mA 6 8 9.5
VVM = 9 V, IVCP = 0 to 10 mA 5.5 7.5 8.5
VVM = 15 V, IVGLS = 0 to 25 mA 9.5 11 12.5

Low-side gate drive voltage VVM = 12 V, IVGLS = 0 to 20 mA 9 10.5 12

VGSL V
with respect to PGND VVM = 10 V, IVGLS = 0 to 15 mA 7.5 9 10.5
VVM = 9 V, IVGLS = 0 to 10 mA 6.5 8 9.5

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at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEAD_TIME = 00b 50
DEAD_TIME = 01b 100
Gate drive SPI Device
tDEAD DEAD_TIME = 10b 200 ns
dead time
DEAD_TIME = 11b 400
H/W Device 100
TDRIVE = 00b 500
TDRIVE = 01b 1000
Peak current SPI Device
tDRIVE TDRIVE = 10b 2000 ns
gate drive time
TDRIVE = 11b 4000
H/W Device 4000
IDRIVEP_HS or IDRIVEP_LS = 0000b 50
IDRIVEP_HS or IDRIVEP_LS = 0001b 50
IDRIVEP_HS or IDRIVEP_LS = 0010b 100
IDRIVEP_HS or IDRIVEP_LS = 0011b 150
IDRIVEP_HS or IDRIVEP_LS = 0100b 300
IDRIVEP_HS or IDRIVEP_LS = 0101b 350
IDRIVEP_HS or IDRIVEP_LS = 0110b 400
IDRIVEP_HS or IDRIVEP_LS = 0111b 450
SPI Device
IDRIVEP_HS or IDRIVEP_LS = 1000b 550
IDRIVEP_HS or IDRIVEP_LS = 1001b 600
IDRIVEP_HS or IDRIVEP_LS = 1010b 650
Peak source
IDRIVEP IDRIVEP_HS or IDRIVEP_LS = 1011b 700 mA
gate current
IDRIVEP_HS or IDRIVEP_LS = 1100b 850
IDRIVEP_HS or IDRIVEP_LS = 1101b 900
IDRIVEP_HS or IDRIVEP_LS = 1110b 950
IDRIVEP_HS or IDRIVEP_LS = 1111b 1000
IDRIVE = Tied to GND 50
IDRIVE = 18 kΩ ± 5% tied to GND 100
IDRIVE = 75 kΩ ± 5% tied to GND 150
H/W Device IDRIVE = Hi-Z 300
IDRIVE = 75 kΩ ± 5% tied to DVDD 450
IDRIVE = 18 kΩ ± 5% tied to DVDD 700
IDRIVE = Tied to DVDD 1000

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at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IDRIVEN_HS or IDRIVEN_LS = 0000b 100
IDRIVEN_HS or IDRIVEN_LS = 0001b 100
IDRIVEN_HS or IDRIVEN_LS = 0010b 200
IDRIVEN_HS or IDRIVEN_LS = 0011b 300
IDRIVEN_HS or IDRIVEN_LS = 0100b 600
IDRIVEN_HS or IDRIVEN_LS = 0101b 700
IDRIVEN_HS or IDRIVEN_LS = 0110b 800
IDRIVEN_HS or IDRIVEN_LS = 0111b 900
SPI Device
IDRIVEN_HS or IDRIVEN_LS = 1000b 1100
IDRIVEN_HS or IDRIVEN_LS = 1001b 1200
IDRIVEN_HS or IDRIVEN_LS = 1010b 1300
Peak sink
IDRIVEN IDRIVEN_HS or IDRIVEN_LS = 1011b 1400 mA
gate current
IDRIVEN_HS or IDRIVEN_LS = 1100b 1700
IDRIVEN_HS or IDRIVEN_LS = 1101b 1800
IDRIVEN_HS or IDRIVEN_LS = 1110b 1900
IDRIVEN_HS or IDRIVEN_LS = 1111b 2000
IDRIVE = Tied to GND 100
IDRIVE = 18 kΩ ± 5% tied to GND 200
IDRIVE = 75 kΩ ± 5% tied to GND 300
H/W Device IDRIVE = Hi-Z 600
IDRIVE = 75 kΩ ± 5% tied to DVDD 900
IDRIVE = 18 kΩ ± 5% tied to DVDD 1400
IDRIVE = Tied to DVDD 2000
Source current after tDRIVE 50
IHOLD Gate holding current mA
Sink current after tDRIVE 100
ISTRONG Gate strong pulldown current GHx to SHx and GLx to SPx/SLx 2 A
ROFF Gate hold off resistor GHx to SHx and GLx to SPx/SLx 150 kΩ
CURRENT SHUNT AMPLIFIER (SNx, SOx, SPx, VREF)
CSA_GAIN = 00b 4.85 5 5.15
CSA_GAIN = 01b 9.7 10 10.3
SPI Device
CSA_GAIN = 10b 19.4 20 20.6
CSA_GAIN = 11b 38.8 40 41.2
GCSA Amplifier gain V/V
GAIN = Tied to GND 4.85 5 5.15
GAIN = 47 kΩ ± 5% tied to GND 9.7 10 10.3
H/W Device
GAIN = Hi-Z 19.4 20 20.6
GAIN = Tied to DVDD 38.8 40 41.2
VO_STEP = 0.5 V, GCSA = 5 V/V 250
VO_STEP = 0.5 V, GCSA = 10 V/V 500
tSET Settling time to ±1% ns
VO_STEP = 0.5 V, GVSA = 20 V/V 1000
VO_STEP = 0.5 V, GCSA = 40 V/V 2000
VCOM Common mode input range –0.15 0.15 V
VDIFF Differential mode input range –0.3 0.3 V
VOFF Input offset error VSP = VSN = 0 V –3 3 mV
VDRIFT Drift offset VSP = VSN = 0 V 10 µV/°C
VVREF –
VLINEAR SOx output voltage linear range 0.25 V
0.25

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at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VVREF –
VSP = VSN = 0 V, VREF_DIV = 0b
0.3
SPI Device
VVREF /
VBIAS SOx output voltage bias VSP = VSN = 0 V, VREF_DIV = 1b V
2
VVREF /
H/W Device VSP = VSN = 0 V
2
IBIAS SPx/SNx input bias current 250 µA
VSLEW SOx output slew rate 60-pF load 10 V/µs
IVREF VREF input current VVREF = 5 V 1.5 2.5 mA
DRV835xF: 60-pF load 10 MHz
UGB Unity gain bandwidth
DRV835xFR: 60-pF load 1 MHz
PROTECTION CIRCUITS
DRV835xF: VM falling, UVLO report 8.0 8.3 8.8
DRV835xF: VM rising, UVLO recovery 8.2 8.5 9.0
VVM_UV VM undervoltage lockout V
DRV835xFR: VM falling, UVLO report 8.0 8.3 8.6
DRV835xFR: VM rising, UVLO recovery 8.2 8.5 8.8
VVM_UVH VM undervoltage hysteresis Rising to falling threshold 200 mV
tVM_UVD VM undervoltage deglitch time VM falling, UVLO report 10 µs
DRV835xF: VDRAIN falling, UVLO report 6.1 6.4 6.8
DRV835xF: VDRAIN rising, UVLO recovery 6.3 6.6 7.0
VVDR_UV VDRAIN undervoltage lockout V
DRV835xFR: VDRAIN falling, UVLO report 6.1 6.4 6.7
DRV835xFR: VDRAIN rising, UVLO recovery 6.3 6.6 6.9
VVDR_UVH VDRAIN undervoltage hysteresis Rising to falling threshold 200 mV
tVDR_UVD VDRAIN undervoltage deglitch time VDRAIN falling, UVLO report 10 µs
VDRAIN
VVCP_UV VCP charge pump undervoltage lockout VCP falling, GDUV report V
+5
VGLS low-side regulator undervoltage
VVGLS_UV VGLS falling, GDUV report 4.25 V
lockout
Positive clamping voltage 12.5 13.5 16
VGS_CLAMP High-side gate clamp V
Negative clamping voltage –0.7

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at TA = –40°C to +125°C, VVM = 9 to 75 V, VVDRAIN = 9 to 100 V, VVIN = 48 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DRV835xF: VDS_LVL = 0000b 0.041 0.06 0.072
DRV835xF: VDS_LVL = 0001b 0.051 0.07 0.084
DRV835xF: VDS_LVL = 0010b 0.061 0.08 0.096
DRV835xF: VDS_LVL = 0011b 0.071 0.09 0.108
DRV835xF: VDS_LVL = 0100b 0.081 0.1 0.115
DRV835xFR: VDS_LVL = 0000b 0.048 0.06 0.072
DRV835xFR: VDS_LVL = 0001b 0.056 0.07 0.084
DRV835xFR: VDS_LVL = 0010b 0.064 0.08 0.096
DRV835xFR: VDS_LVL = 0011b 0.072 0.09 0.108
DRV835xFR: VDS_LVL = 0100b 0.085 0.1 0.115
SPI Device VDS_LVL = 0101b 0.18 0.2 0.22 V
VDS_LVL = 0110b 0.27 0.3 0.33
VDS_LVL = 0111b 0.36 0.4 0.44
VDS_LVL = 1000b 0.45 0.5 0.55

VDS overcurrent VDS_LVL = 1001b 0.54 0.6 0.66

VVDS_OCP
trip voltage VDS_LVL = 1010b 0.63 0.7 0.77
VDS_LVL = 1011b 0.72 0.8 0.88
VDS_LVL = 1100b 0.81 0.9 0.99
VDS_LVL = 1101b 0.9 1.0 1.1
VDS_LVL = 1110b 1.35 1.5 1.65
VDS_LVL = 1111b 1.8 2 2.2
DRV835xF: VDS = Tied to GND 0.041 0.06 0.072
DRV835xF: VDS = 18 kΩ ± 5% tied to GND 0.081 0.1 0.115
DRV835xFR: VDS = Tied to GND 0.048 0.06 0.072
DRV835xFR: VDS = 18 kΩ ± 5% tied to GND 0.085 0.1 0.115
H/W Device VDS = 75 kΩ ± 5% tied to GND 0.18 0.2 0.22 V
VDS = Hi-Z 0.36 0.4 0.44
VDS = 75 kΩ ± 5% tied to DVDD 0.63 0.7 0.77
VDS = 18 kΩ ± 5% tied to DVDD 0.9 1 1.1
VDS = Tied to DVDD Disabled
OCP_DEG = 00b 1
OCP_DEG = 01b 2
VDS and VSENSE SPI Device
tOCP_DEG OCP_DEG = 10b 4 µs
overcurrent deglitch time
OCP_DEG = 11b 8
H/W Device 4
SEN_LVL = 00b 0.25
SEN_LVL = 01b 0.5
VSENSE overcurrent trip SPI Device
VSEN_OCP SEN_LVL = 10b 0.75 V
voltage
SEN_LVL = 11b 1
H/W Device 1
TRETRY = 0b 8 ms
SPI Device
tRETRY Overcurrent retry time TRETRY = 1b 50 μs
H/W Device 8 ms
TOTW Thermal warning temperature Die temperature, TJ 130 150 170 °C
TOTSD Thermal shutdown temperature Die temperature, TJ 150 170 190 °C
THYS Thermal hysteresis Die temperature, TJ 20 °C

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7.6 SPI Timing Requirements

at TA = –40°C to +125°C, VVM = 9 to 75 V (unless otherwise noted)
MIN NOM MAX UNIT
tREADY SPI ready after enable VM > UVLO, ENABLE = 3.3 V 1 ms
tCLK SCLK minimum period 100 ns
tCLKH SCLK minimum high time 50 ns
tCLKL SCLK minimum low time 50 ns
tSU_SDI SDI input data setup time 20 ns
tH_SDI SDI input data hold time 30 ns
tD_SDO SDO output data delay time SCLK high to SDO valid 30 ns
tSU_nSCS nSCS input setup time 50 ns
tH_nSCS nSCS input hold time 50 ns
tHI_nSCS nSCS minimum high time before active low 400 ns
tDIS_nSCS nSCS disable time nSCS high to SDO high impedance 10 ns

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7.7 Typical Characteristics

10 2
TA = 40°C
TA = 25°C 1.95
9.5 TA = 125°C 1.9
Operating Current (mA)

Supply Current (mA)

1.85
9
1.8

8.5 1.75
1.7
8 1.65
1.6 TA = 40°C
7.5
1.55 TA = 25°C
TA = 125°C
7 1.5
0 10 20 30 40 50 60 70 80 0 10 20 30 40 50 60 70 80 90 100
Supply Voltage (V) Supply Voltage (V) D002
D001

VVM = VVDRAIN VVM = VVDRAIN

Figure 7-1. VM Supply Current Over Supply Figure 7-2. VDRAIN Supply Current Over Supply
Voltage Voltage
40 40
TA = 40°C VSUP = 9 V
TA = 25°C VSUP = 48 V
35 TA = 125°C 35 VSUP = 100 V
Sleep Current (PA)
Sleep Current (PA)

30 30

25 25

20 20

15 15

10 10
0 10 20 30 40 50 60 70 80 90 100 -40 -20 0 20 40 60 80 100 120 140
Supply Voltage (V) D003
Temperature (qC) D004

IVM + IVDRAIN IVM + IVDRAIN

Figure 7-3. Sleep Current Over Supply Voltage Figure 7-4. Sleep Current Over Temperature
11 15.5
TA = 40qC TA = 40qC
10.9 TA = 25qC 15.4 TA = 25qC
10.8 TA = 125qC 15.3 TA = 125qC

10.7 15.2
VGLS Voltage (V)
VCP Voltage (V)

10.6 15.1
10.5 15
10.4 14.9
10.3 14.8
10.2 14.7
10.1 14.6
10 14.5
0 5 10 15 20 25 0 5 10 15 20 25
VCP Load Current (mA) D005
VGLS Load Current (mA) D006

VVM = 48-V VVM = 48-V

Figure 7-5. VCP Voltage Over Load Figure 7-6. VGLS Voltage Over Load Current

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11 16
TA = 40qC TA = 40qC
10.9 TA = 25qC 15.8 TA = 25qC
10.8 TA = 125qC 15.6 TA = 125qC

10.7 15.4

VGLS Voltage (V)

VCP Voltage (V)

10.6 15.2
10.5 15
10.4 14.8
10.3 14.6
10.2 14.4
10.1 14.2
10 14
0 5 10 15 20 25 0 5 10 15 20 25
VCP Load Current (mA) D007
VGLS Load Current (mA) D008

VVM = 15-V VVM = 15-V

Figure 7-7. VCP Voltage Over Load Current Figure 7-8. VGLS Voltage Over Load Current
11 13
TA = 40qC TA = 40qC
10.8 TA = 25qC 12.8 TA = 25qC
10.6 TA = 25qC 12.6 TA = 125qC

10.4 12.4
VGLS Voltage (V)
VCP Voltage (V)

10.2 12.2
10 12
9.8 11.8
9.6 11.6
9.4 11.4
9.2 11.2
9 11
0 5 10 15 20 0 5 10 15 20
VCP Load Current (mA) D009
VGLS Load Current (mA) D010

VVM = 12-V VVM = 12-V

Figure 7-9. VCP Voltage Over Load Current Figure 7-10. VGLS Voltage Over Load Current
9 10
TA = 40qC TA = 40qC
8.8 TA = 25qC 9.8 TA = 25qC
8.6 TA = 125qC 9.6 TA = 125qC

8.4 9.4
VGLS Voltage (V)
VCP Voltage (V)

8.2 9.2
8 9
7.8 8.8
7.6 8.6
7.4 8.4
7.2 8.2
7 8
0 2 4 6 8 10 0 2 4 6 8 10
VCP Load Current (mA) VGLS Load Current (mA) D012
D011

VVM = 9-V VVM = 9-V

Figure 7-11. VCP Voltage Over Load Current Figure 7-12. VGLS Voltage Over Load Current

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8 Detailed Description
8.1 Overview
The DRV835xF family of devices are integrated 100-V gate drivers for three-phase motor drive applications.
These devices decrease system component count, cost, and complexity by integrating three independent half-
bridge gate drivers, charge pump and linear regulator for the high-side and low-side gate driver supply voltages,
and optional triple current shunt amplifiers. A standard serial peripheral interface (SPI) provides a simple method
for configuring the various device settings and reading fault diagnostic information through an external controller.
Alternatively, a hardware interface (H/W) option allows for configuring the most commonly used settings through
fixed external resistors.
The gate drivers support external N-channel high-side and low-side power MOSFETs and can drive up to 1-A
source, 2-A sink peak currents with a 25-mA average output current. The high-side gate drive supply voltage
is generated using a doubler charge-pump architecture that regulates the VCP output to VVDRAIN + 10.5-V.
The low-side gate drive supply voltage is generated using a linear regulator from the VM power supply that
regulates the VGLS output to 14.5-V. The VGLS supply is further regulated to 11-V on the GLx low-side gate
driver outputs. A smart gate-drive architecture provides the ability to dynamically adjust the output gate-drive
current strength allowing for the gate driver to control the power MOSFET VDS switching speed. This allows for
the removal of external gate drive resistors and diodes reducing BOM component count, cost, and PCB area.
The architecture also uses an internal state machine to protect against gate-drive short-circuit events, control the
half-bridge dead time, and protect against dV/dt parasitic turnon of the external power MOSFET.
The gate drivers can operate in either a single or dual supply architecture. In the single supply architecture, VM
can be tied to VDRAIN and is regulated to the correct supply voltages internally. In the dual supply architecture,
VM can be connected to a lower voltage supply from a more efficient switching regulator to improve the device
efficiency. VDRAIN stays connected to the external MOSFETs to set the correct charge pump and overcurrent
monitor reference.
The DRV8353F devices integrate three, bidirectional current-shunt amplifiers for monitoring the current level
through each of the external half-bridges using a low-side shunt resistor. The gain setting of the shunt amplifier
can be adjusted through the SPI or hardware interface with the SPI providing additional flexibility to adjust the
output bias point.
In addition to the high level of device integration, the DRV835xF family of devices provides a wide range of
integrated protection features. These features include power-supply undervoltage lockout (UVLO), gate drive
undervoltage lockout (GDUV), VDS overcurrent monitoring (OCP), gate-driver short-circuit detection (GDF), and
overtemperature shutdown (OTW/OTSD). Fault events are indicated by the nFAULT pin with detailed information
available in the SPI registers on the SPI device version.
The DRV835xF family of devices are available in 0.5-mm pin pitch, QFN surface-mount packages. The QFN
sizes are 5 × 5 mm for the 32-pin package and 6 × 6 mm for the 40-pin package.

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8.2 Functional Block Diagram

VM VDRAIN
VM VDRAIN
>10 …F 0.1 …F
VCP
VCP GHA
HS
1 …F CPH VCP
Charge SHA
VDRAIN Pump VGLS
47 nF CPL
GLA
LS

VGLS VGLS
SLA
Linear
Regulator Gate Driver
1 …F DVDD
DVDD VDRAIN
1 …F Linear VCP
Regulator
GND GHB
Power Supplies HS

SHB
ENABLE
VGLS
Digital GLB
INHA Core LS

SLB
INLA
Gate Driver

INHB VDRAIN
Smart Gate VCP
INLB Drive GHC
Control HS
Inputs Protection
INHC SHC
VGLS
INLC
GLC
LS
MODE SLC

IDRIVE Gate Driver

VCC

VDS RPU
Fault Output nFAULT

Figure 8-1. Block Diagram for DRV8350FH

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VM VDRAIN
VM VDRAIN
>10 …F 0.1 …F
VCP
VCP GHA
HS
1 …F CPH VCP
Charge SHA
VDRAIN Pump VGLS
47 nF CPL
GLA
LS

VGLS VGLS
SLA
Linear
Regulator Gate Driver
1 …F DVDD
DVDD VDRAIN
1 …F Linear VCP
Regulator
GND GHB
Power Supplies HS

SHB
ENABLE
VGLS
Digital GLB
INHA Core LS

SLB
INLA
Gate Driver

INHB Control VDRAIN

Inputs Smart Gate VCP
INLB Drive GHC
HS
Protection
INHC SHC
VGLS
INLC
GLC
LS
SDI
VCC SPI SLC

RPU Gate Driver

SDO VCC

RPU
SCLK Fault Output nFAULT

nSCS

Figure 8-2. Block Diagram for DRV8350FS

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VM VDRAIN
VM VDRAIN
>10 …F 0.1 …F
VCP
VCP GHA
HS
1 …F CPH VCP
Charge SHA
VDRAIN Pump VGLS
47 nF CPL
GLA
LS

VGLS VGLS
SPA
Linear
Regulator Gate Driver
1 …F DVDD
DVDD VDRAIN
1 …F Linear VCP
Regulator
GND GHB
Power Supplies HS

SHB
ENABLE
VGLS
Digital GLB
INHA Core LS

SPB
INLA
Gate Driver

INHB VDRAIN
Smart Gate VCP
INLB Drive GHC
HS
Control Protection
INHC SHC
Inputs
VGLS
INLC
GLC
LS
MODE SPC

IDRIVE Gate Driver

VCC
RPU
VDS Fault Output nFAULT

GAIN

VCC SPC
VREF
0.1 …F AV SNC RSENC
SOC
SPB
SOB Output
Offset AV SNB RSENB
SOA Bias
SPA
AGND
AV SNA RSENA

Figure 8-3. Block Diagram for DRV8353FH

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VM VDRAIN
VM VDRAIN
>10 …F 0.1 …F
VCP
VCP GHA
HS
1 …F CPH VCP
Charge SHA
VDRAIN Pump VGLS
47 nF CPL
GLA
LS

VGLS VGLS
SPA
Linear
Regulator Gate Driver
1 …F DVDD
DVDD VDRAIN
1 …F Linear VCP
Regulator
GND GHB
Power Supplies HS

SHB
ENABLE
VGLS
Digital GLB
INHA Core LS

SPB
INLA
Gate Driver

INHB Control VDRAIN

Inputs Smart Gate VCP
INLB Drive GHC
HS
Protection
INHC SHC
VGLS
INLC
GLC
LS
SDI
VCC SPI SPC

RPU Gate Driver

SDO VCC
RPU
SCLK Fault Output nFAULT

nSCS

VCC SPC
VREF
0.1 …F AV SNC RSENC
SOC
SPB
SOB Output
Offset AV SNB RSENB
SOA Bias
SPA
AGND
AV SNA RSENA

Figure 8-4. Block Diagram for DRV8353FS

8.3 Feature Description

8.3.1 Three Phase Smart Gate Drivers
The DRV835xF family of devices integrates three, half-bridge gate drivers, each capable of driving high-side and
low-side N-channel power MOSFETs. The VCP doubler charge pump provides the correct gate bias voltage to
the high-side MOSFET across a wide operating voltage range in addition to providing 100% duty-cycle support.
The internal VGLS linear regulator provides the gate-bias voltage for the low-side MOSFETs. The half-bridge
gate drivers can be used in combination to drive a three-phase motor or separately to drive other types of loads.

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The DRV835xF family of devices implement a smart gate-drive architecture which allows the user to dynamically
adjust the gate drive current without requiring external gate current limiting resistors. Additionally, this
architecture provides a variety of protection features for the external MOSFETs including automatic dead-time
insertion, parasitic dV/dt gate turnon prevention, and gate-fault detection.
8.3.1.1 PWM Control Modes
The DRV835xF family of devices provides four different PWM control modes to support various commutation
and control methods. Texas Instruments does not recommend changing the MODE pin or PWM_MODE register
during operation of the power MOSFETs. Set all INHx and INLx pins to logic low before making a MODE or
PWM_MODE change.
8.3.1.1.1 6x PWM Mode (PWM_MODE = 00b or MODE Pin Tied to AGND)
In this mode, each half-bridge supports three output states: low, high, or high-impedance (Hi-Z). The
corresponding INHx and INLx signals control the output state as listed in Table 8-1.
Table 8-1. 6x PWM Mode Truth Table
INLx INHx GLx GHx SHx
0 0 L L Hi-Z
0 1 L H H
1 0 H L L
1 1 L L Hi-Z

8.3.1.1.2 3x PWM Mode (PWM_MODE = 01b or MODE Pin = 47 kΩ to AGND)

In this mode, the INHx pin controls each half-bridge and supports two output states: low or high. The INLx pin is
used to change the half-bridge to high impedance. If the high-impedance (Hi-Z) sate is not required, tie all INLx
pins logic high. The corresponding INHx and INLx signals control the output state as listed in Table 8-2.
Table 8-2. 3x PWM Mode Truth Table
INLx INHx GLx GHx SHx
0 X L L Hi-Z
1 0 H L L
1 1 L H H

8.3.1.1.3 1x PWM Mode (PWM_MODE = 10b or MODE Pin = Hi-Z)

In this mode, the DRV835xF family of devices uses 6-step block commutation tables that are stored internally.
This feature allows for a three-phase BLDC motor to be controlled using a single PWM sourced from a simple
controller. The PWM is applied on the INHA pin and determines the output frequency and duty cycle of the
half-bridges.
The half-bridge output states are managed by the INLA, INHB, and INLB pins which are used as state logic
inputs. The state inputs can be controlled by an external controller or connected directly to hall sensor digital
outputs from the motor (INLA = HALL_A, INHB = HALL_B, INLB = HALL_C). The 1x PWM mode usually
operates with synchronous rectification, however it can be configured to use asynchronous diode freewheeling
rectification on SPI devices. This configuration is set using the 1PWM_COM bit through the SPI registers.
The INHC input controls the direction through the 6-step commutation table which is used to change the
direction of the motor when hall sensors are directly controlling the INLA, INHB, and INLB state inputs. Tie the
INHC pin low if this feature is not required.
The INLC input brakes the motor by turning off all high-side MOSFETs and turning on all low-side MOSFETs
when it is pulled low. This brake is independent of the states of the other input pins. Tie the INLC pin high if this
feature is not required.

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Table 8-3. Synchronous 1x PWM Mode

LOGIC AND HALL INPUTS GATE-DRIVE OUTPUTS
INHC = 0 INHC = 1 PHASE A PHASE B PHASE C
STATE DESCRIPTION
INLA INHB INLB INLA INHB INLB GHA GLA GHB GLB GHC GLC
Stop 0 0 0 0 0 0 L L L L L L Stop
Align 1 1 1 1 1 1 PWM !PWM L H L H Align
1 1 1 0 0 0 1 L L PWM !PWM L H B→C
2 1 0 0 0 1 1 PWM !PWM L L L H A→C
3 1 0 1 0 1 0 PWM !PWM L H L L A→B
4 0 0 1 1 1 0 L L L H PWM !PWM C→B
5 0 1 1 1 0 0 L H L L PWM !PWM C→A
6 0 1 0 1 0 1 L H PWM !PWM L L B→A

Table 8-4. Asynchronous 1x PWM Mode 1PWM_COM = 1 (SPI Only)

LOGIC AND HALL INPUTS GATE-DRIVE OUTPUTS
INHC = 0 INHC = 1 PHASE A PHASE B PHASE C
STATE DESCRIPTION
INLA INHB INLB INLA INHB INLB GHA GLA GHB GLB GHC GLC
Stop 0 0 0 0 0 0 L L L L L L Stop
Align 1 1 1 1 1 1 PWM L L H L H Align
1 1 1 0 0 0 1 L L PWM L L H B→C
2 1 0 0 0 1 1 PWM L L L L H A→C
3 1 0 1 0 1 0 PWM L L H L L A→B
4 0 0 1 1 1 0 L L L H PWM L C→B
5 0 1 1 1 0 0 L H L L PWM L C→A
6 0 1 0 1 0 1 L H PWM L L L B→A

Figure 8-5 and Figure 8-6 show the different possible configurations in 1x PWM mode.

INHA
MCU_PWM PWM
INLA
MCU_GPIO STATE0
INHB
MCU_GPIO STATE1
BLDC Motor
INLB
MCU_GPIO STATE2
INHC
MCU_GPIO DIR
INLC
MCU_GPIO nBRAKE

Figure 8-5. 1x PWM—Simple Controller

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INHA
MCU_PWM PWM
INLA H
STATE0
INHB
STATE1 H
BLDC Motor
INLB
STATE2
H
INHC
MCU_GPIO DIR
INLC
MCU_GPIO nBRAKE

Figure 8-6. 1x PWM—Hall Sensor

8.3.1.1.4 Independent PWM Mode (PWM_MODE = 11b or MODE Pin Tied to DVDD)
In this mode, the corresponding input pin independently controls each high-side and low-side gate driver. This
control mode allows for the external controller to bypass the internal dead-time handshake of the DRV835xF or
to utilize the high-side and low-side drivers to drive separate high-side and low-side loads with each half-bridge.
These types of loads include unidirectional brushed DC motors, solenoids, and low-side and high-side switches.
In this mode, If the system is configured in a half-bridge configuration, shoot-through occurs when the high-side
and low-side MOSFETs are turned on at the same time.
Table 8-5. Independent PWM Mode Truth Table
INLx INHx GLx GHx
0 0 L L
0 1 L H
1 0 H L
1 1 H H

Because the high-side and low-side VDS overcurrent monitors share the SHx sense line, using both of the
monitors is not possible if both the high-side and low-side gate drivers are being operated independently.
In this case, connect the SHx pin to the high-side driver and disable the VDS overcurrent monitors as shown in
Figure 8-7.

Disable
+
VDS
±
VM
VDRAIN

VCP
GHx Load
INHx HS

SHx
VGLS
INLx
GLx
LS

Load

Gate Driver SLx/SPx

Disable
+
VDS
±

Figure 8-7. Independent PWM High-Side and Low-Side Drivers

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If the half-bridge is used to implement only a high-side or low-side driver, using the VDS overcurrent monitors
is still possible. Connect the SHx pin as shown in Figure 8-8 or Figure 8-9. The unused gate driver and the
corresponding input can be left disconnected.

+
VDS
±
VM
VDRAIN
VCP
GHx
INHx HS

SHx
VGLS
INLx
GLx
LS Load

Gate Driver SLx/SPx

+
VDS ±

Figure 8-8. Single High-Side Driver

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+
VDS
±
VM
VDRAIN
VCP
GHx Load
INHx HS

SHx
VGLS
INLx
GLx
LS

Gate Driver SLx/SPx

+
VDS ±

Figure 8-9. Single Low-Side Driver

8.3.1.2 Device Interface Modes

The DRV835xF family of devices support two different interface modes (SPI and hardware) to allow the end
application to design for either flexibility or simplicity. The two interface modes share the same four pins, allowing
the different versions to be pin to pin compatible. This allows for application designers to evaluate with one
interface version and potentially switch to another with minimal modifications to their design.
8.3.1.2.1 Serial Peripheral Interface (SPI)
The SPI devices support a serial communication bus that allows for an external controller to send and receive
data with the DRV835xF. This allows for the external controller to configure device settings and read detailed
fault information. The interface is a four wire interface utilizing the SCLK, SDI, SDO, and nSCS pins.
• The SCLK pin is an input which accepts a clock signal to determine when data is captured and propagated
on SDI and SDO.
• The SDI pin is the data input.
• The SDO pin is the data output. The SDO pin uses an open-drain structure and requires an external pullup
resistor.
• The nSCS pin is the chip select input. A logic low signal on this pin enables SPI communication with the
DRV835xF.
For more information on the SPI, see the Section 8.5.1 section.
8.3.1.2.2 Hardware Interface
Hardware interface devices convert the four SPI pins into four resistor configurable inputs, GAIN, IDRIVE,
MODE, and VDS. This allows for the application designer to configure the most commonly used device settings
by tying the pin logic high or logic low, or with a simple pullup or pulldown resistor. This removes the requirement
for an SPI bus from the external controller. General fault information can still be obtained through the nFAULT
pin.
• The GAIN pin configures the current shunt amplifier gain.
• The IDRIVE pin configures the gate drive current strength.
• The MODE pin configures the PWM control mode.
• The VDS pin configures the voltage threshold of the VDS overcurrent monitors.
For more information on the hardware interface, see the Section 8.3.3 section.

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SCLK SPI
Interface

SDI

VCC

RPU
SDO

nSCS

Figure 8-10. SPI

DVDD DVDD

RGAIN
GAIN Hardware
Interface
DVDD
DVDD
IDRIVE

DVDD

MODE

DVDD

VDS

RVDS

Figure 8-11. Hardware Interface

8.3.1.3 Gate Driver Voltage Supplies and Input Supply Configurations

The high-side gate-drive voltage supply is created using a doubler charge pump that operates from the VM and
VDRAIN voltage supply inputs. The charge pump allows the gate driver to correctly bias the high-side MOSFET
gate with respect to the source across a wide input supply voltage range. The charge pump is regulated to keep
a fixed output voltage of VVDRAIN + 10.5 V and supports an average output current of 25 mA. When VVM is less
than 12 V, the charge pump operates in full doubler mode and generates VVCP = 2 × VVM – 1.5 V with respect
to VVDRAIN when unloaded. The charge pump is continuously monitored for undervoltage to prevent under-driven
MOSFET conditions.
The charge pump requires a X5R or X7R, 1-µF, 16-V ceramic capacitor between the VDRAIN and VCP pins
to act as the storage capacitor. Additionally, a X5R or X7R, 47-nF, VDRAIN-rated ceramic capacitor is required
between the CPH and CPL pins to act as the flying capacitor.

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VDRAIN
VDRAIN

1 …F
VCP

CPH

VM
47 nF Charge
Pump
Control
CPL

Figure 8-12. Charge Pump Architecture

The low-side gate drive voltage is created using a linear regulator that operates from the VM voltage supply
input. The VGLS linear regulator allows the gate driver to correctly bias the low-side MOSFET gate with respect
to ground. The VGLS linear regulator output is fixed at 14.5 V and further regulated to 11-V on the GLx outputs
during operation. The VGLS regulator supports an output current of 25 mA. The VGLS linear regulator is
monitored for undervoltage to prevent under driver MOSFET conditions. The VGLS linear regulator requires a
X5R or X7R, 1-µF, 16-V ceramic capacitor between VGLS and GND.
Since the charge pump output is regulated to VVDRAIN + 10.5 V this allows for VM to be supplied either directly
from the high voltage motor supply (up to 75 V) to support a single supply system or from a low voltage gate
driver power supply derived from a switching or linear regulator to improve the device efficiency or utilize an
externally available power supply. Figure 8-13 and Figure 8-14 show examples of the DRV835xF configured in
either single supply or dual supply configuration.

48-V
Power
Supply

VM VDRAIN

DRV835xF
Power
MOSFETs

Figure 8-13. Single Supply Example

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48-V
Power
Supply

48-V to 15-V
DC/DC

VM VDRAIN

DRV835xF
Power
MOSFETs

Figure 8-14. Dual Supply Example

8.3.1.4 Smart Gate Drive Architecture

The DRV835xF gate drivers use an adjustable, complimentary, push-pull topology for both the high-side and
low-side drivers. This topology allows for both a strong pullup and pulldown of the external MOSFET gates.
Additionally, the gate drivers use a smart gate-drive architecture to provide additional control of the external
power MOSFETs, take additional steps to protect the MOSFETs, and allow for optimal tradeoffs between
efficiency and robustness. This architecture is implemented through two components called IDRIVE and TDRIVE
which are detailed in the Section 8.3.1.4.1 section and Section 8.3.1.4.2 section. Figure 8-15 shows the high-
level functional block diagram of the gate driver.
The IDRIVE gate-drive current and TDRIVE gate-drive time should be initially selected based on the parameters
of the external power MOSFET used in the system and the desired rise and fall times (see the Section 9
section).
The high-side gate driver also implements a Zener clamp diode to help protect the external MOSFET gate from
overvoltage conditions in the case of external short-circuit events on the MOSFET.

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INHx VCP
VDRAIN

Control
Inputs
INLx GHx
Level
Shifters

150 k
SHx

+
VGS
±

VGLS

Digital
Core
Level GLx
Shifters

150 k

SLx/SPx

+
VGS
±

Figure 8-15. Gate Driver Block Diagram

8.3.1.4.1 IDRIVE: MOSFET Slew-Rate Control

The IDRIVE component implements adjustable gate-drive current to control the MOSFET VDS slew rates.
The MOSFET VDS slew rates are a critical factor for optimizing radiated emissions, energy and duration of
diode recovery spikes, dV/dt gate turnon leading to shoot-through, and switching voltage transients related to
parasitics in the external half-bridge. IDRIVE operates on the principal that the MOSFET VDS slew rates are
predominately determined by the rate of gate charge (or gate current) delivered during the MOSFET QGD or
Miller charging region. By allowing the gate driver to adjust the gate current, it can effectively control the slew
rate of the external power MOSFETs.
IDRIVE allows the DRV835xF family of devices to dynamically switch between gate drive currents either through
a register setting on SPI devices or the IDRIVE pin on hardware interface devices. The SPI devices provide
16 IDRIVE settings ranging between 50-mA to 1-A source and 100-mA to 2-A sink. Hardware interface devices
provides 7 IDRIVE settings between the same ranges. The gate drive current setting is delivered to the gate
during the turnon and turnoff of the external power MOSFET for the tDRIVE duration. After the MOSFET turnon or
turnoff, the gate driver switches to a smaller hold IHOLD current to improve the gate driver efficiency. Additional
details on the IDRIVE settings are described in the Section 8.6 section for the SPI devices and in the Section
8.3.3 section for the hardware interface devices.
8.3.1.4.2 TDRIVE: MOSFET Gate Drive Control
The TDRIVE component is an integrated gate-drive state machine that provides automatic dead time insertion
through switching handshaking, parasitic dV/dt gate turnon prevention, and MOSFET gate-fault detection.
The first component of the TDRIVE state machine is automatic dead-time insertion. Dead time is period of time
between the switching of the external high-side and low-side MOSFETs to make sure that they do not cross
conduct and cause shoot-through. The DRV835xF family of devices use VGS voltage monitors to measure the
MOSFET gate-to-source voltage and determine the correct time to switch instead of relying on a fixed time
value. This feature allows the gate-driver dead time to adjust for variation in the system such a temperature
drift and variation in the MOSFET parameters. An additional digital dead time (tDEAD) can be inserted and is
adjustable through the registers on SPI devices.

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The automatic dead-time insertion has a limitation when the gate driver is transitioning from high-side MOSFET
on to low-side MOSFET on when the phase current is coming into the external half-bridge. In this case, the
high-side diode will conduct during the dead-time and hold up the switch-node voltage to VDRAIN. In this case,
an additional delay of approximately 100-200 ns is introduced into the dead-time handshake. This is introduced
due to the need to discharge the voltage present on the internal VGS detection circuit.
The second component focuses on parasitic dV/dt gate turnon prevention. To implement this, the TDRIVE state
machine enables a strong pulldown ISTRONG current on the opposite MOSFET gate whenever a MOSFET is
switching. The strong pulldown last for the TDRIVE duration. This feature helps remove parasitic charge that
couples into the MOSFET gate when the half-bridge switch-node voltage slews rapidly.
The third component implements a gate-fault detection scheme to detect pin-to-pin solder defects, a MOSFET
gate failure, or a MOSFET gate stuck-high or stuck-low voltage condition. This implementation is done with a
pair of VGS gate-to-source voltage monitors for each half-bridge gate driver. When the gate driver receives a
command to change the state of the half-bridge it starts to monitor the gate voltage of the external MOSFET. If
at the end of the tDRIVE period the VGS voltage has not reached the correct threshold the gate driver will report
a fault. To make sure that a false fault is not detected, a tDRIVE time should be selected that is longer than the
time required to charge or discharge the MOSFET gate. The tDRIVE time does not increase the PWM time and
will terminate if another PWM command is received while active. Additional details on the TDRIVE settings are
described in the Section 8.6 section for SPI devices and in the Section 8.3.3 section for hardware interface
devices.
Figure 8-16 shows an example of the TDRIVE state machine in operation.

VINHx

VINLx

VGHx

tDEAD tDEAD

IHOLD IDRIVE IHOLD ISTRONG IHOLD

IGHx
IDRIVE IHOLD

tDRIVE tDRIVE

VGLx

tDEAD tDEAD

IHOLD IDRIVE IHOLD ISTRONG IHOLD

IGLx
IDRIVE IHOLD

tDRIVE tDRIVE

Figure 8-16. TDRIVE State Machine

8.3.1.4.3 Propagation Delay

The propagation delay time (tpd) is measured as the time between an input logic edge to a detected output
change. This time has three parts consisting of the digital input deglitcher delay, the digital propagation delay,
and the delay through the analog gate drivers.
The input deglitcher prevents high-frequency noise on the input pins from affecting the output state of the gate
drivers. To support multiple control modes and dead time insertion, a small digital delay is added as the input
command propagates through the device. Lastly, the analog gate drivers have a small delay that contributes to
the overall propagation delay of the device.

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8.3.1.4.4 MOSFET VDS Monitors

The gate drivers implement adjustable VDS voltage monitors to detect overcurrent or short-circuit conditions on
the external power MOSFETs. When the monitored voltage is greater than the VDS trip point (VVDS_OCP) for
longer than the deglitch time (tOCP), an overcurrent condition is detected and action is taken according to the
device VDS fault mode.
The high-side VDS monitors measure the voltage between the VDRAIN and SHx pins. In devices with three
current-shunt amplifiers (DRV8353F), the low-side VDS monitors measure the voltage between the SHx and
SPx pins. If the current shunt amplifier is unused, tie the SP pins to the common ground point of the external
half-bridges. On device options without the current shunt amplifiers (DRV8350F) the low-side VDS monitor
measures between the SHx and SLx pins.
For the SPI devices, the low-side VDS monitor reference point can be changed between the SPx and SNx pins
if desired with the LS_REF register setting. This is only for the low-side VDS monitor. The high-side VDS monitor
stays between the VDRAIN and SHx pins.
The VVDS_OCP threshold is programmable between 0.06 V and 2 V on SPI device and between 0.06 V and 1 V
on hardware interface devices. Additional information on the VDS monitor levels are described in the Section 8.6
section for SPI devices and in the Section 8.3.3 section hardware interface device.
VDRAIN
VDRAIN
+
+ VDS
VDS ±
± VVDS_OCP
GHx

SHx
+
+ VDS
VDS ±
± VVDS_OCP GLx

SLx

Figure 8-17. DRV8350F VDS Monitors

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VDRAIN
VDRAIN
+
+ VDS
VDS ±
± VVDS_OCP
GHx

SHx
+
+ VDS
VDS ±
± VVDS_OCP GLx

SPx

0
RSENSE
1 SNx
LS_REF
(SPI Only)

Figure 8-18. DRV8353F VDS Monitors

8.3.1.4.5 VDRAIN Sense and Reference Pin

The DRV835xF family of devices provides a separate sense and reference pin for the common point of the
high-side MOSFET drain. This pin is called VDRAIN. This pin allows the sense line for the overcurrent monitors
(VDRAIN) and the power supply (VM) to stay separate and prevent noise on the VDRAIN sense line.
The VDRAIN pin serves as the reference point for the integrated charge pump. This makes sure that the charge
pump reference stays with respect to the power MOSFET supply through voltage transient conditions.
Since the charge pump is referenced to VDRAIN, this also allows for VM to supplied either directed from the
power MOSFET supply (VDRAIN) or from an independent supply. This allows for a configuration where VM can
be supplied from an efficient low voltage supply to increase the device efficiency.
8.3.2 DVDD Linear Voltage Regulator
A 5-V, 10-mA linear regulator is integrated into the DRV835xF family of devices and is available for use by
external circuitry. This regulator can provide the supply voltage for low-current supporting circuitry. The output of
the DVDD regulator should be bypassed near the DVDD pin with a X5R or X7R, 1-µF, 6.3-V ceramic capacitor
routed directly back to the adjacent DGND or GND ground pin.
The DVDD nominal, no-load output voltage is 5 V. When the DVDD load current exceeds 10 mA, the regulator
functions like a constant-current source. The output voltage drops significantly with a current load greater than
10 mA.
VM

REF +
± DVDD 5 V, 10 mA

GND/ 1 …F
DGND

Figure 8-19. DVDD Linear Regulator Block Diagram

Use Equation 1 to calculate the power dissipated in the device because of the DVDD linear regulator.

P VVM VDVDD u IDVDD (1)

For example, at VVM = 24 V, drawing 20 mA out of DVDD results in a power dissipation as shown in Equation 2.
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P 24 V 3.3 V u 20 mA 414 mW (2)

8.3.3 Pin Diagrams

Figure 8-20 shows the input structure for the logic-level pins, INHx, INLx, ENABLE, nSCS, SCLK, and SDI.

DVDD

STATE RESISTANCE INPUT

VIH Tied to DVDD Logic High

VIL Tied to AGND Logic Low

100 k

Figure 8-20. Logic-Level Input Pin Structure

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Figure 8-21 shows the structure of the four level input pins, MODE and GAIN, on hardware interface devices.
The input can be set with an external resistor.

MODE GAIN

DVDD
STATE RESISTANCE DVDD Independent 40 V/V
+
VI4 Tied to DVDD
50 k ±
Hi-Z (>500 kŸ WR 1x PWM 20V/V
VI3
AGND)
+
47 NŸ “5% 84 k
VI2
to AGND ±
3x PWM 10 V/V
VI1 Tied to AGND
+

±
6x PWM 5 V/V

Figure 8-21. Four Level Input Pin Structure

Figure 8-22 shows the structure of the seven level input pins, IDRIVE and VDS, on hardware interface devices.
The input can be set with an external resistor.

IDRIVE VDS

1/2 A Disabled
+

±
STATE RESISTANCE
700/1400 mA 1V
VI7 Tied to DVDD DVDD +
DVDD
±
18 k ± 5%
VI6
to DVDD 450/900 mA 0.7 V

75 k ± 5% 73 k +
VI5
to DVDD
±
Hi-Z (>500 kŸ
VI4 300/600 mA 0.4 V
to AGND) 73 k
+
75 k ± 5%
VI3
to AGND ±
18 NŸ “5% 150/300 mA 0.2 V
VI2
to AGND
+

VI1 Tied to AGND ±

100/200 mA 0.1 V
+

±
50/100 mA 0.06 V

Figure 8-22. Seven Level Input Pin Structure

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Figure 8-23 shows the structure of the open-drain output pins nFAULT and SDO. The open-drain output requires
an external pullup resistor to function correctly.

DVDD

STATE STATUS RPU

No Fault Inactive OUTPUT

Fault Active Active

Inactive

Figure 8-23. Open-Drain Output Pin Structure

8.3.4 Low-Side Current-Shunt Amplifiers (DRV8353F)

The DRV8353F integrate three, high-performance low-side current-shunt amplifiers for current measurements
using low-side shunt resistors in the external half-bridges. Low-side current measurements are commonly used
to implement overcurrent protection, external torque control, or brushless DC commutation with the external
controller. All three amplifiers can be used to sense the current in each of the half-bridge legs or one amplifier
can be used to sense the sum of the half-bridge legs. The current shunt amplifiers include features such
as programmable gain, offset calibration, unidirectional and bidirectional support, and a voltage reference pin
(VREF).
8.3.4.1 Bidirectional Current Sense Operation
The SOx pin on the DRV8353F outputs an analog voltage equal to the voltage across the SPx and SNx pins
multiplied by the gain setting (GCSA). The gain setting is adjustable between four different levels (5 V/V, 10 V/V,
20 V/V, and 40 V/V). Use Equation 3 to calculate the current through the shunt resistor.

VVREF
VSOx
I 2
GCSA u RSENSE (3)

R2

R3

R4

R5
SOx R6 I

R1 SPx
VCC ±
R1 RSENSE
VREF +
SNx
0.1 …F R2

½ + R3
±
R4

R5

Figure 8-24. Bidirectional Current-Sense Configuration

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SO (V)

VREF

VVREF / 2
VLINEAR

SP ± SN (V)

Figure 8-25. Bidirectional Current-Sense Output

I

SP
SO R
AV

SN

SO
VREF
SP ± SN
VVREF ± 0.25 V ±0.3 V

±I × R
VSO(range±)

VSO(off)max
VOFF,
VVREF / 2 0V
VDRIFT
VSO(off)min

VSO(range+)
I×R

0.25 V 0.3 V

0V

Figure 8-26. Bidirectional Current Sense Regions

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8.3.4.2 Unidirectional Current Sense Operation (SPI only)

On the DRV8353F SPI devices, use the VREF_DIV bit to remove the VREF divider. In this case the shunt
amplifier operates unidirectionally and SOx outputs an analog voltage equal to the voltage across the SPx and
SNx pins multiplied by the gain setting (GCSA). Use Equation 4 to calculate the current through the shunt resistor.

VVREF VSOx
I
GCSA u RSENSE (4)

R2

R3

R4

R5
SOx R6 I

R1 SPx
±
R1 RSENSE
+
VCC SNx
R2
VREF
+ R3
0.1 …F
±
R4

R5

Figure 8-27. Unidirectional Current-Sense Configuration

SO (V)

VREF

VVREF ± 0.3 V

VLINEAR

SP ± SN (V)

Figure 8-28. Unidirectional Current-Sense Output

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SP
SO R
AV

SN

SO
VREF

VVREF ± 0.25 V

VSO(off)max
VOFF, SP ± SN
VVREF ± 0.3 V 0V
VDRIFT
VSO(off)min

VSO(range)
I×R

0.3 V

0.25 V

0V

Figure 8-29. Unidirectional Current-Sense Regions

8.3.4.3 Amplifier Calibration Modes

To minimize DC offset and drift over temperature, a DC calibration mode is provided and enabled through the
SPI register (CSA_CAL_X). This option is not available on hardware interface devices. When the calibration
setting is enabled the inputs to the amplifier are shorted and the load is disconnected. DC calibration can be
done at any time, even when the half-bridges are operating. For the best results, do the DC calibration during the
switching OFF period to decrease the potential noise impact to the amplifier. A diagram of the calibration mode is
shown below. When a CSA_CAL_X bit is enabled, the corresponding amplifier goes to the calibration mode.

RF

SOx ROUT
RSP !CAL SP
-
RSN !CAL RSENSE
SN
VREF +

+ CAL CAL
RG

Figure 8-30. Amplifier Manual Calibration

In addition to the manual calibration method provided on the SPI devices versions, the DRV835xF family of
devices provide an auto calibration feature on both the hardware and SPI device versions in order to minimize
the amplifier input offset after power up and during run time to account for temperature and device variation.
Auto calibration occurs automatically on device power up for both the hardware and SPI device options. The
power up auto calibration starts immediately after the VREF pin crosses the minimum operational VREF voltage.
50 us should be allowed for the power up auto calibration routine to complete after the VREF pin voltage crosses

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the minimum VREF operational voltage. The auto calibration functions by doing a trim routine of the amplifier to
minimize the amplifier input offset. After this the amplifiers are ready for normal operation.
For the SPI device options, auto calibration can also be done again during run time by enabling the AUTO_CAL
register setting. Auto calibration can then be commanded with the corresponding CSA_CAL_X register setting to
rerun the auto calibration routine. During auto calibration all of the amplifiers will be configured for the max gain
setting in order to improve the accuracy of the calibration routine.
8.3.4.4 MOSFET VDS Sense Mode (SPI Only)
The current-sense amplifiers on the DRV8353F SPI devices can be configured to amplify the voltage across the
external low-side MOSFET VDS. This allows for the external controller to measure the voltage drop across the
MOSFET RDS(on) without the shunt resistor and then calculate the half-bridge current level.
To enable this mode set the CSA_FET bit to 1. The positive input of the amplifier is then internally connected to
the SHx pin with an internal clamp to prevent high voltage on the SHx pin from damaging the sense amplifier
inputs. During this mode of operation, the SPx pins should stay connected to the source of the low-side
MOSFET as it serves as the reference for the low-side gate driver. When the CSA_FET bit is set to 1, the
negative reference for the low-side VDS monitor is automatically set to SNx, regardless of the state of the
LS_REF bit state. This setting is implemented to prevent disabling of the low-side VDS monitor.
If the system operates in MOSFET VDS sensing mode, route the SHx and SNx pins with Kelvin connections
across the drain and source of the external low-side MOSFETs.
VDRAIN

High-Side VDRAIN
VDS Monitor VCP

+
VDS
±
GHx

(SPI only)

CSA_FET = 0
SHx
LS_REF = 0

VGLS
Low-Side
VDS Monitor
+
VDS GLx
±
0
1

10 k
10 k SPx
SOx
AV RSEN
10 k
SNx

GND

Figure 8-31. Resistor Sense Configuration

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VDRAIN

VDRAIN
High-Side
VDS Monitor VCP

+
VDS
±
GHx

(SPI only)

CSA_FET = 1
SHx

LS_REF = X

VGLS
Low-Side
VDS Monitor

+
VDS GLx
±
0
1

10 k
10 k SPx

SOx
AV
10 k SNx

GND

Figure 8-32. VDS Sense Configuration

When operating in MOSFET VDS sense mode, the amplifier is enabled at the end of the tDRIVE time. At this
time, the amplifier input is connected to the SHx pin, and the SOx output is valid. When the low-side MOSFET
receives a signal to turn off, the amplifier inputs, SPx and SNx, are shorted together internally.
8.3.5 Gate Driver Protective Circuits
The DRV835xF family of devices are fully protected against VM undervoltage, charge pump and low-side
regulator undervoltage, MOSFET VDS overcurrent, gate driver shorts, and overtemperature events.
8.3.5.1 VM Supply and VDRAIN Undervoltage Lockout (UVLO)
If at any time the input supply voltage on the VM pin falls below the VVM_UV threshold or voltage on VDRAIN
pin falls below the VVDR_UV, all of the external MOSFETs are disabled, the charge pump is disabled, and the
nFAULT pin is driven low. The FAULT and UVLO bits are also latched high in the registers on SPI devices.
Normal operation continues (gate driver operation and the nFAULT pin is released) when the undervoltage
condition is removed. The UVLO bit stays set until cleared through the CLR_FLT bit or an ENABLE pin reset
pulse (tRST).
VM supply or VDRAIN undervoltage may also lead to VCP charge pump or VGLS regulator undervoltage
conditions to report. This behavior is expected because the VCP and VGLS supply voltages are dependent on
VM and VDRAIN pin voltages.
8.3.5.2 VCP Charge-Pump and VGLS Regulator Undervoltage Lockout (GDUV)
If at any time the voltage on the VCP pin (charge pump) falls below the VVCP_UV threshold or voltage on the
VGLS pin falls below the VVGLS_UV threshold, all of the external MOSFETs are disabled and the nFAULT pin is
driven low. The FAULT and GDUV bits are also latched high in the registers on SPI devices. Normal operation
continues (gate-driver operation and the nFAULT pin is released) when the undervoltage condition is removed.

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The GDUV bit stays set until cleared through the CLR_FLT bit or an ENABLE pin reset pulse (tRST). Setting
the DIS_GDUV bit high on the SPI devices disables this protection feature. On hardware interface devices, the
GDUV protection is always enabled.
8.3.5.3 MOSFET VDS Overcurrent Protection (VDS_OCP)
A MOSFET overcurrent event is sensed by monitoring the VDS voltage drop across the external MOSFET
RDS(on). If the voltage across an enabled MOSFET exceeds the VVDS_OCP threshold for longer than the tOCP_DEG
deglitch time, a VDS_OCP event is recognized and action is done according to the OCP_MODE. On hardware
interface devices, the VVDS_OCP threshold is set with the VDS pin, the tOCP_DEG is fixed at 4 µs, and the
OCP_MODE is configured for 8-ms automatic retry but can be disabled by tying the VDS pin to DVDD. On
SPI devices, the VVDS_OCP threshold is set through the VDS_LVL SPI register, the tOCP_DEG is set through the
OCP_DEG SPI register, and the OCP_MODE bit can operate in four different modes: VDS latched shutdown,
VDS automatic retry, VDS report only, and VDS disabled.
The MOSFET VDS overcurrent protection operates in cycle-by-cycle (CBC) mode by default. This can be
disabled on SPI device variants through the SPI registers. When in cycle-by-cycle (CBC) mode a new rising
edge on the PWM inputs will clear an existing overcurrent fault.
Additionally, on SPI devices the OCP_ACT register setting can be set to change the VDS_OCP overcurrent
response between linked and individual shutdown modes. When OCP_ACT is 0, a VDS_OCP fault will only
effect the half-bridge in which it occurred. When OCP_ACT is 1, all three half-bridges will respond to a
VDS_OCP fault on any of the other half-bridges. OCP_ACT defaults to 0, individual shutdown mode.
8.3.5.3.1 VDS Latched Shutdown (OCP_MODE = 00b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation continues (gate driver operation and the nFAULT pin is released) when the VDS_OCP condition is
removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.5.3.2 VDS Automatic Retry (OCP_MODE = 01b)
After a VDS_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven low.
The FAULT, VDS_OCP, and corresponding MOSFET OCP bits are latched high in the SPI registers. Normal
operation continues automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT, VDS_OCP, and MOSFET OCP bits stay latched until the tRETRY period expires.
8.3.5.3.3 VDS Report Only (OCP_MODE = 10b)
No protective action occurs after a VDS_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT, VDS_OCP, and corresponding MOSFET OCP bits high in the
SPI registers. The gate drivers continue to operate as normal. The external controller manages the overcurrent
condition by acting appropriately. The reporting clears (nFAULT pin is released) when the VDS_OCP condition is
removed and a clear faults command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.5.3.4 VDS Disabled (OCP_MODE = 11b)
No action occurs after a VDS_OCP event in this mode.
8.3.5.4 VSENSE Overcurrent Protection (SEN_OCP)
Half-bridge overcurrent is also monitored by sensing the voltage drop across the external current-sense resistor
with the SP pin. If at any time, the voltage on the SP input of the current-sense amplifier exceeds the VSEN_OCP
threshold for longer than the tOCP_DEG deglitch time, a SEN_OCP event is recognized and action is done
according to the OCP_MODE. On hardware interface devices, the VSENSE threshold is fixed at 1 V, tOCP_DEG
is fixed at 4 µs, and the OCP_MODE for VSENSE is fixed for 8-ms automatic retry. On SPI devices, the VSENSE
threshold is set through the SEN_LVL SPI register, the tOCP_DEG is set through the OCP_DEG SPI register,
and the OCP_MODE bit can operate in four different modes: VSENSE latched shutdown, VSENSE automatic retry,
VSENSE report only, and VSENSE disabled.

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The VSENSE overcurrent protection operates in cycle-by-cycle (CBC) mode by default. This can be disabled on
SPI device variants through the SPI registers. When in cycle-by-cycle (CBC) mode a new rising edge on the
PWM inputs will clear an existing overcurrent fault.
Additionally, on SPI devices the OCP_ACT register setting can be set to change the SEN_OCP overcurrent
response between linked and individual shutdown modes. When OCP_ACT is 0, a SEN_OCP fault will only
effect the half-bridge in which it occurred. When OCP_ACT is 1, all three half-bridges will respond to a
SEN_OCP fault on any of the other half-bridges. OCP_ACT defaults to 0, individual shutdown mode.
8.3.5.4.1 VSENSE Latched Shutdown (OCP_MODE = 00b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven
low. The FAULT and SEN_OCP bits are latched high in the SPI registers. Normal operation continues (gate
driver operation and the nFAULT pin is released) when the SEN_OCP condition is removed and a clear faults
command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.5.4.2 VSENSE Automatic Retry (OCP_MODE = 01b)
After a SEN_OCP event in this mode, all the external MOSFETs are disabled and the nFAULT pin is driven
low. The FAULT, SEN_OCP, and corresponding sense OCP bits are latched high in the SPI registers. Normal
operation continues automatically (gate driver operation and the nFAULT pin is released) after the tRETRY time
elapses. The FAULT , SEN_OCP, and sense OCP bits stay latched until the tRETRY period expires.
8.3.5.4.3 VSENSE Report Only (OCP_MODE = 10b)
No protective action occurs after a SEN_OCP event in this mode. The overcurrent event is reported by driving
the nFAULT pin low and latching the FAULT and SEN_OCP bits high in the SPI registers. The gate drivers
continue to operate. The external controller manages the overcurrent condition by acting appropriately. The
reporting clears (nFAULT released) when the SEN_OCP condition is removed and a clear faults command is
issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST).
8.3.5.4.4 VSENSE Disabled (OCP_MODE = 11b or DIS_SEN = 1b)
No action occurs after a SEN_OCP event in this mode. The SEN_OCP bit can be disabled independently of the
VDS_OCP bit by using the DIS_SEN SPI register.
8.3.5.5 Gate Driver Fault (GDF)
The GHx and GLx pins are monitored such that if the voltage on the external MOSFET gate does not increase
or decrease after the tDRIVE time, a gate driver fault is detected. This fault may be encountered if the GHx or
GLx pins are shorted to the PGND, SHx, or VM pins. Additionally, a gate driver fault may be encountered if the
selected IDRIVE setting is not sufficient to turn on the external MOSFET within the tDRIVE period. After a gate
drive fault is detected, all external MOSFETs are disabled and the nFAULT pin driven low. In addition, the FAULT,
GDF, and corresponding VGS bits are latched high in the SPI registers. Normal operation continues (gate driver
operation and the nFAULT pin is released) when the gate driver fault condition is removed and a clear faults
command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). On SPI devices, setting the
DIS_GDF_UVLO bit high disables this protection feature.
Gate driver faults can indicate that the selected IDRIVE or tDRIVE settings are too low to slew the external
MOSFET in the desired time. Increasing either the IDRIVE or tDRIVE setting can resolve gate driver faults in these
cases. Alternatively, if a gate-to-source short occurs on the external MOSFET, a gate driver fault is reported
because of the MOSFET gate not turning on.
8.3.5.6 Overcurrent Soft Shutdown (OCP Soft)
In the case of a MOSFET VDS or VSENSE overcurrent fault the driver uses a special shutdown sequence to
protect the driver and MOSFETs from large voltage switching transients. These large voltage transients can be
created when rapidly switching off the external MOSFETs when a large drain to source current is present, such
as during an overcurrent event.
To mitigate this issue, the DRV835xF family of devices reduce the IDRIVEN pull down current setting for both the
high-side and low-side gate drivers during the MOSFET turn off in response to the fault event. If the programmed

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IDRIVEN value is less than 1100 mA, the IDRIVEN value is set to the minimum IDRIVEN setting. If the programmed
IDRIVEN value is greater than or equal to 1100mA, the IDRIVEN value is reduced by seven code settings.
8.3.5.7 Thermal Warning (OTW)
If the die temperature exceeds the trip point of the thermal warning (TOTW), the OTW bit is set in the registers
of SPI devices. The device does no additional action and continues to function. When the die temperature falls
below the hysteresis point of the thermal warning, the OTW bit clears automatically. The OTW bit can also
be configured to report on the nFAULT pin and FAULT bit by setting the OTW_REP bit to 1 through the SPI
registers.
8.3.5.8 Thermal Shutdown (OTSD)
If the die temperature exceeds the trip point of the thermal shutdown limit (TOTSD), all the external MOSFETs are
disabled, the charge pump is shut down, and the nFAULT pin is driven low. In addition, the FAULT and TSD bits
are latched high. Normal operation continues (gate driver operation and the nFAULT pin is released) when the
overtemperature condition is removed. The TSD bit stays latched high indicating that a thermal event occurred
until a clear fault command is issued either through the CLR_FLT bit or an ENABLE reset pulse (tRST). This
protection feature cannot be disabled.
8.3.5.9 Fault Response Table
Table 8-6. Fault Action and Response
FAULT CONDITION CONFIGURATION REPORT GATE DRIVER RECOVERY
VM Undervoltage Automatic:
VVM < VVM_UV — nFAULT Hi-Z
(VM_UV) VVM > VVM_UV
VDRAIN Undervoltage Automatic:
VVDRAIN < VVDR_UV — nFAULT Hi-Z
(VDR_UV) VVM > VVDR_UV

Charge Pump Undervoltage DIS_GDUV = 0b nFAULT Hi-Z Automatic:

VVCP < VVCP_UV
(VCP_UV) DIS_GDUV = 1b None Active VVCP > VVCP_UV

VGLS Regulator Undervoltage DIS_GDUV = 0b nFAULT Hi-Z Automatic:

VVGLS < VVGLS_UV
(VGLS_UV) DIS_GDUV = 1b None Active VVGLS > VVGLS_UV

Latched:
OCP_MODE = 00b nFAULT Hi-Z
CLR_FLT, ENABLE Pulse

VDS Overcurrent Retry:

VDS > VVDS_OCP OCP_MODE = 01b nFAULT Hi-Z
(VDS_OCP) tRETRY
OCP_MODE = 10b nFAULT Active No action
OCP_MODE = 11b None Active No action
Latched:
OCP_MODE = 00b nFAULT Hi-Z
CLR_FLT, ENABLE Pulse
Retry:
VSENSE Overcurrent OCP_MODE = 01b nFAULT Hi-Z
VSP > VSEN_OCP tRETRY
(SEN_OCP)
OCP_MODE = 10b nFAULT Active No action
OCP_MODE = 11b or
None Active No action
DIS_SEN = 1b
Latched:
Gate Driver Fault DIS_GDF = 0b nFAULT Hi-Z
VGS Stuck > tDRIVE CLR_FLT, ENABLE Pulse
(GDF)
DIS_GDF = 1b None Active No action
Automatic:
Thermal Warning OTW_REP = 1b nFAULT Active
TJ > TOTW TJ < TOTW – THYS
(OTW)
OTW_REP = 0b None Active No action
Thermal Shutdown Automatic:
TJ > TOTSD — nFAULT Hi-Z
(OTSD) TJ < TOTSD – THYS

8.4 Device Functional Modes

8.4.1 Gate Driver Functional Modes
8.4.1.1 Sleep Mode
The ENABLE pin manages the state of the DRV835xF family of devices. When the ENABLE pin is low, the
device goes to a low-power sleep mode. In sleep mode, all gate drivers are disabled, all external MOSFETs are
disabled, the VCP charge pump and VGLS regulator are disabled, the DVDD regulator is disabled, the sense
amplifiers are disabled, and the SPI bus is disabled. In sleep mode all the device registers will reset to their
default values. The tSLEEP time must elapse after a falling edge on the ENABLE pin before the device goes to

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sleep mode. The device comes out of sleep mode automatically if the ENABLE pin is pulled high. The tWAKE time
must elapse before the device is ready for inputs.
In sleep mode and when VVM < VUVLO, all external MOSFETs are disabled. The high-side gate pins, GHx, are
pulled to the SHx pin by an internal resistor and the low-side gate pins, GLx, are pulled to the PGND pin by an
internal resistor.
8.4.1.2 Operating Mode
When the ENABLE pin is high and VVM > VUVLO, the device goes to operating mode. The tWAKE time must
elapse before the device is ready for inputs. In this mode the charge pump, low-side gate regulator, DVDD
regulator, and SPI bus are active
8.4.1.3 Fault Reset (CLR_FLT or ENABLE Reset Pulse)
In the case of device latched faults, the DRV835xF family of devices goes to a partial shutdown state to help
protect the external power MOSFETs and system.
When the fault condition has been removed the device can reenter the operating state by either setting the
CLR_FLT SPI bit on SPI devices or issuing a result pulse to the ENABLE pin on either interface variant. The
ENABLE reset pulse (tRST) consists of a high-to-low-to-high transition on the ENABLE pin. The low period of the
sequence should fall with the tRST time window or else the device will start the complete shutdown sequence.
The reset pulse has no effect on any of the regulators, device settings, or other functional blocks
8.5 Programming
This section applies only to the DRV835xF SPI devices.
8.5.1 SPI Communication
8.5.1.1 SPI
On DRV835xF SPI devices, an SPI bus is used to set device configurations, operating parameters, and read out
diagnostic information. The SPI operates in slave mode and connects to a master controller. The SPI input data
(SDI) word consists of a 16 bit word, with a 5 bit command and 11 bits of data. The SPI output data (SDO) word
consists of 11-bit register data. The first 5 bits are don’t care bits.
A valid frame must meet the following conditions:
• The SCLK pin should be low when the nSCS pin transitions from high to low and from low to high.
• The nSCS pin should be pulled high for at least 400 ns between words.
• When the nSCS pin is pulled high, any signals at the SCLK and SDI pins are ignored and the SDO pin is set
Hi-Z.
• Data is captured on the falling edge of SCLK and data is propagated on the rising edge of SCLK.
• The most significant bit (MSB) is shifted in and out first.
• A full 16 SCLK cycles must occur for transaction to be valid.
• If the data word sent to the SDI pin is not 16 bits, a frame error occurs and the data word is ignored.
• For a write command, the existing data in the register being written to is shifted out on the SDO pin following
the 5 bit command data.
• The SDO pin is an open-drain output and requires an external pullup resistor.
8.5.1.1.1 SPI Format
The SDI input data word is 16 bits long and consists of the following format:
• 1 read or write bit, W (bit B15)
• 4 address bits, A (bits B14 through B11)
• 11 data bits, D (bits B11 through B0)
Set the read/write bit (W0, B15) to 0b for a write command. Set the read/write bit (W0, B15) to 1b for a read
command.
The SDO output data word is 16 bits long and the first 5 bits are don't care bits. The response word is the data
currently in the register being accessed.

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Table 8-7. SDI Input Data Word Format

R/W ADDRESS DATA
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
W0 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 8-8. SDO Output Data Word Format

DON'T CARE BITS DATA
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
X X X X X D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

nSCS

SCLK

SDI X MSB LSB X

SDO Z MSB LSB Z

Capture
Point

Propagate
Point

Figure 8-33. SPI Slave Timing Diagram

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8.6 Register Maps

This section applies only to the DRV835xF SPI devices.

Note
Do not modify reserved registers or addresses not listed in the register maps . Writing to these registers may have unintended effects. For
all reserved bits, the default value is 0. To help prevent erroneous SPI writes from the master controller, set the LOCK bits to lock the SPI
registers.

Table 8-9. Register Map

Name 10 9 8 7 6 5 4 3 2 1 0 Type Address
DRV8350FS
Fault Status 1 FAULT VDS_OCP GDF UVLO OTSD VDS_HA VDS_LA VDS_HB VDS_LB VDS_HC VDS_LC R 0h
VGS Status 2 SA_OC SB_OC SC_OC OTW GDUV VGS_HA VGS_LA VGS_HB VGS_LB VGS_HC VGS_LC R 1h
Driver Control OCP_ACT DIS_GDUV DIS_GDF OTW_REP PWM_MODE 1PWM_COM 1PWM_DIR COAST BRAKE CLR_FLT RW 2h
Gate Drive HS LOCK IDRIVEP_HS IDRIVEN_HS RW 3h
Gate Drive LS CBC TDRIVE IDRIVEP_LS IDRIVEN_LS RW 4h
OCP Control TRETRY DEAD_TIME OCP_MODE OCP_DEG VDS_LVL RW 5h
Reserved Reserved RW 6h
Reserved Reserved RW 7h
DRV8353FS
Fault Status 1 FAULT VDS_OCP GDF UVLO OTSD VDS_HA VDS_LA VDS_HB VDS_LB VDS_HC VDS_LC R 0h
VGS Status 2 SA_OC SB_OC SC_OC OTW GDUV VGS_HA VGS_LA VGS_HB VGS_LB VGS_HC VGS_LC R 1h
Driver Control OCP_ACT DIS_GDUV DIS_GDF OTW_REP PWM_MODE 1PWM_COM 1PWM_DIR COAST BRAKE CLR_FLT RW 2h
Gate Drive HS LOCK IDRIVEP_HS IDRIVEN_HS RW 3h
Gate Drive LS CBC TDRIVE IDRIVEP_LS IDRIVEN_LS RW 4h
OCP Control TRETRY DEAD_TIME OCP_MODE OCP_DEG VDS_LVL RW 5h
CSA Control CSA_FET VREF_DIV LS_REF CSA_GAIN DIS_SEN CSA_CAL_A CSA_CAL_B CSA_CAL_C SEN_LVL RW 6h
Reserved Reserved CAL_MODE RW 7h

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8.6.1 Status Registers

The status registers are used to reporting warning and fault conditions. The status registers are read-only
registers
Complex bit access types are encoded to fit into small table cells. Table 8-10 shows the codes that are used for
access types in this section.
Table 8-10. Status Registers Access Type Codes
Access Type Code Description
Read Type
R R Read
Reset or Default Value
-n Value after reset or the default value

8.6.1.1 Fault Status Register 1 (address = 0x00h)

The fault status register 1 is shown in Figure 8-34 and described in Table 8-11.
Register access type: Read only
Figure 8-34. Fault Status Register 1
10 9 8 7 6 5 4 3 2 1 0
FAULT VDS_OCP GDF UVLO OTSD VDS_HA VDS_LA VDS_HB VDS_LB VDS_HC VDS_LC
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b

Table 8-11. Fault Status Register 1 Field Descriptions

Bit Field Type Default Description
10 FAULT R 0b Logic OR of FAULT status registers. Mirrors nFAULT pin.
9 VDS_OCP R 0b Indicates VDS monitor overcurrent fault condition
8 GDF R 0b Indicates gate drive fault condition
7 UVLO R 0b Indicates undervoltage lockout fault condition
6 OTSD R 0b Indicates overtemperature shutdown
5 VDS_HA R 0b Indicates VDS overcurrent fault on the A high-side MOSFET
4 VDS_LA R 0b Indicates VDS overcurrent fault on the A low-side MOSFET
3 VDS_HB R 0b Indicates VDS overcurrent fault on the B high-side MOSFET
2 VDS_LB R 0b Indicates VDS overcurrent fault on the B low-side MOSFET
1 VDS_HC R 0b Indicates VDS overcurrent fault on the C high-side MOSFET
0 VDS_LC R 0b Indicates VDS overcurrent fault on the C low-side MOSFET

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8.6.1.2 Fault Status Register 2 (address = 0x01h)

The fault status register 2 is shown in Figure 8-35 and described in Table 8-12.
Register access type: Read only
Figure 8-35. Fault Status Register 2
10 9 8 7 6 5 4 3 2 1 0
SA_OC SB_OC SC_OC OTW GDUV VGS_HA VGS_LA VGS_HB VGS_LB VGS_HC VGS_LC
R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b R-0b

Table 8-12. Fault Status Register 2 Field Descriptions

Bit Field Type Default Description
10 SA_OC R 0b Indicates overcurrent on phase A sense amplifier (DRV8353xS
DRV8353xS-Q1)
9 SB_OC R 0b Indicates overcurrent on phase B sense amplifier (DRV8353xS
DRV8353xS-Q1)
8 SC_OC R 0b Indicates overcurrent on phase C sense amplifier (DRV8353xS
DRV8353xS-Q1)
7 OTW R 0b Indicates overtemperature warning
6 GDUV R 0b Indicates VCP charge pump and/or VGLS undervoltage fault
condition
5 VGS_HA R 0b Indicates gate drive fault on the A high-side MOSFET
4 VGS_LA R 0b Indicates gate drive fault on the A low-side MOSFET
3 VGS_HB R 0b Indicates gate drive fault on the B high-side MOSFET
2 VGS_LB R 0b Indicates gate drive fault on the B low-side MOSFET
1 VGS_HC R 0b Indicates gate drive fault on the C high-side MOSFET
0 VGS_LC R 0b Indicates gate drive fault on the C low-side MOSFET

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8.6.2 Control Registers

The control registers are used to configure the device. The control registers are read and write capable
Complex bit access types are encoded to fit into small table cells. Table 8-13 shows the codes that are used for
access types in this section.
Table 8-13. Control Registers Access Type Codes
Access Type Code Description
Read Type
R R Read
Write Type
W W Write
Reset or Default Value
-n Value after reset or the default value

8.6.2.1 Driver Control Register (address = 0x02h)

The driver control register is shown in Figure 8-36 and described in Table 8-14.
Register access type: Read/Write
Figure 8-36. Driver Control Register
10 9 8 7 6 5 4 3 2 1 0
OCP DIS DIS OTW 1PWM 1PWM CLR
PWM_MODE COAST BRAKE
_ACT _GDUV _GDF _REP _COM _DIR _FLT
R/W-0b R/W-0b R/W-0b R/W-0b R/W-00b R/W-0b R/W-0b R/W-0b R/W-0b R/W-0b

Table 8-14. Driver Control Field Descriptions

Bit Field Type Default Description
10 OCP_ACT R/W 0b 0b = Associated half-bridge is shutdown in response to
VDS_OCP and SEN_OCP
1b = All three half-bridges are shutdown in response to
VDS_OCP and SEN_OCP
9 DIS_GDUV R/W 0b 0b =VCP and VGLS undervoltage lockout fault is enabled
1b = VCP and VGLS undervoltage lockout fault is disabled
8 DIS_GDF R/W 0b 0b = Gate drive fault is enabled
1b = Gate drive fault is disabled
7 OTW_REP R/W 0b 0b = OTW is not reported on nFAULT or the FAULT bit
1b = OTW is reported on nFAULT and the FAULT bit
6-5 PWM_MODE R/W 00b 00b = 6x PWM Mode
01b = 3x PWM mode
10b = 1x PWM mode
11b = Independent PWM mode
4 1PWM_COM R/W 0b 0b = 1x PWM mode uses synchronous rectification
1b = 1x PWM mode uses asynchronous rectification
3 1PWM_DIR R/W 0b In 1x PWM mode this bit is ORed with the INHC (DIR) input
2 COAST R/W 0b Write a 1 to this bit to put all MOSFETs in the Hi-Z state
1 BRAKE R/W 0b Write a 1 to this bit to turn on all three low-side MOSFETs
This bit is ORed with the INLC (BRAKE) input in 1x PWM mode.
0 CLR_FLT R/W 0b Write a 1 to this bit to clear latched fault bits.
This bit automatically resets after being writen.

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8.6.2.2 Gate Drive HS Register (address = 0x03h)

The gate drive HS register is shown in Figure 8-37 and described in Table 8-15.
Register access type: Read/Write
Figure 8-37. Gate Drive HS Register
10 9 8 7 6 5 4 3 2 1 0
LOCK IDRIVEP_HS IDRIVEn_HS
R/W-011b R/W-1111b R/W-1111b

Table 8-15. Gate Drive HS Field Descriptions

Bit Field Type Default Description
10-8 LOCK R/W 011b Write 110b to lock the settings by ignoring further register writes
except to these bits and address 0x02h bits 0-2.
Writing any sequence other than 110b has no effect when
unlocked.
Write 011b to this register to unlock all registers.
Writing any sequence other than 011b has no effect when
locked.
7-4 IDRIVEP_HS R/W 1111b 0000b = 50 mA
0001b = 50 mA
0010b = 100 mA
0011b = 150 mA
0100b = 300 mA
0101b = 350 mA
0110b = 400 mA
0111b = 450 mA
1000b = 550 mA
1001b = 600 mA
1010b = 650 mA
1011b = 700 mA
1100b = 850 mA
1101b = 900 mA
1110b = 950 mA
1111b = 1000 mA
3-0 IDRIVEN_HS R/W 1111b 0000b = 100 mA
0001b = 100 mA
0010b = 200 mA
0011b = 300 mA
0100b = 600 mA
0101b = 700 mA
0110b = 800 mA
0111b = 900 mA
1000b = 1100 mA
1001b = 1200 mA
1010b = 1300 mA
1011b = 1400 mA
1100b = 1700 mA
1101b = 1800 mA
1110b = 1900 mA
1111b = 2000 mA

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8.6.2.3 Gate Drive LS Register (address = 0x04h)

The gate drive LS register is shown in Figure 8-38 and described in Table 8-16.
Register access type: Read/Write
Figure 8-38. Gate Drive LS Register
10 9 8 7 6 5 4 3 2 1 0
CBC TDRIVE IDRIVEP_LS IDRIVEN_LS
R/W-1b R/W-11b R/W-1111b R/W-1111b

Table 8-16. Gate Drive LS Register Field Descriptions

Bit Field Type Default Description
10 CBC R/W 1b Active only when OCP_MODE = 01b
0b = For VDS_OCP and SEN_OCP, the fault is cleared after
tRETRY
1b = For VDS_OCP and SEN_OCP, the fault is cleared when
a new PWM input is given or after tRETRY
9-8 TDRIVE R/W 11b 00b = 500-ns peak gate-current drive time
01b = 1000-ns peak gate-current drive time
10b = 2000-ns peak gate-current drive time
11b = 4000-ns peak gate-current drive time
7-4 IDRIVEP_LS R/W 1111b 0000b = 50 mA
0001b = 50 mA
0010b = 100 mA
0011b = 150 mA
0100b = 300 mA
0101b = 350 mA
0110b = 400 mA
0111b = 450 mA
1000b = 550 mA
1001b = 600 mA
1010b = 650 mA
1011b = 700 mA
1100b = 850 mA
1101b = 900 mA
1110b = 950 mA
1111b = 1000 mA
3-0 IDRIVEN_LS R/W 1111b 0000b = 100 mA
0001b = 100 mA
0010b = 200 mA
0011b = 300 mA
0100b = 600 mA
0101b = 700 mA
0110b = 800 mA
0111b = 900 mA
1000b = 1100 mA
1001b = 1200 mA
1010b = 1300 mA
1011b = 1400 mA
1100b = 1700 mA
1101b = 1800 mA
1110b = 1900 mA
1111b = 2000 mA

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8.6.2.4 OCP Control Register (address = 0x05h)

The OCP control register is shown in Figure 8-39 and described in Table 8-17.
Register access type: Read/Write
Figure 8-39. OCP Control Register
10 9 8 7 6 5 4 3 2 1 0
TRETRY DEAD_TIME OCP_MODE OCP_DEG VDS_LVL
R/W-0b R/W-01b R/W-01b R/W-01b R/W-1101b

Table 8-17. OCP Control Field Descriptions

Bit Field Type Default Description
10 TRETRY R/W 0b 0b = VDS_OCP and SEN_OCP retry time is 8 ms
1b = VDS_OCP and SEN_OCP retry time is 50 µs
9-8 DEAD_TIME R/W 01b 00b = 50-ns dead time
01b = 100-ns dead time
10b = 200-ns dead time
11b = 400-ns dead time
7-6 OCP_MODE R/W 01b 00b = Overcurrent causes a latched fault
01b = Overcurrent causes an automatic retrying fault
10b = Overcurrent is report only but no action is taken
11b = Overcurrent is not reported and no action is taken
5-4 OCP_DEG R/W 10b 00b = Overcurrent deglitch of 1 µs
01b = Overcurrent deglitch of 2 µs
10b = Overcurrent deglitch of 4 µs
11b = Overcurrent deglitch of 8 µs
3-0 VDS_LVL R/W 1001b 0000b = 0.06 V
0001b = 0.07 V
0010b = 0.08 V
0011b = 0.09 V
0100b = 0.1 V
0101b = 0.2 V
0110b = 0.3 V
0111b = 0.4 V
1000b = 0.5 V
1001b = 0.6 V
1010b = 0.7 V
1011b = 0.8 V
1100b = 0.9 V
1101b = 1 V
1110b = 1.5 V
1111b = 2 V

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8.6.2.5 CSA Control Register (DRV8353FOnly) (address = 0x06h)

The CSA control register is shown in Figure 8-40 and described in Table 8-18.
Register access type: Read/Write
This register is only available with the DRV8353F family of devices.
Figure 8-40. CSA Control Register
10 9 8 7 6 5 4 3 2 1 0
CSA VREF LS CSA DIS CSA CSA CSA SEN
_FET _DIV _REF _GAIN _SEN _CAL_A _CAL_B _CAL_C _LVL
R/W-0b R/W-1b R/W-0b R/W-10b R/W-0b R/W-0b R/W-0b R/W-0b R/W-11b

Table 8-18. CSA Control Field Descriptions

Bit Field Type Default Description
10 CSA_FET R/W 0b 0b = Sense amplifier positive input is SPx
1b = Sense amplifier positive input is SHx (also automatically
sets the LS_REF bit to 1)
9 VREF_DIV R/W 1b 0b = Sense amplifier reference voltage is VREF (unidirectional
mode)
1b = Sense amplifier reference voltage is VREF divided by 2
8 LS_REF R/W 0b 0b = VDS_OCP for the low-side MOSFET is measured
across SHx to SPx
1b = VDS_OCP for the low-side MOSFET is measured across
SHx to SNx
7-6 CSA_GAIN R/W 10b 00b = 5-V/V shunt amplifier gain
01b = 10-V/V shunt amplifier gain
10b = 20-V/V shunt amplifier gain
11b = 40-V/V shunt amplifier gain
5 DIS_SEN R/W 0b 0b = Sense overcurrent fault is enabled
1b = Sense overcurrent fault is disabled
4 CSA_CAL_A R/W 0b 0b = Normal sense amplifier A operation
1b = Short inputs to sense amplifier A for offset calibration
3 CSA_CAL_B R/W 0b 0b = Normal sense amplifier B operation
1b = Short inputs to sense amplifier B for offset calibration
2 CSA_CAL_C R/W 0b 0b = Normal sense amplifier C operation
1b = Short inputs to sense amplifier C for offset calibration
1-0 SEN_LVL R/W 11b 00b = Sense OCP 0.25 V
01b = Sense OCP 0.5 V
10b = Sense OCP 0.75 V
11b = Sense OCP 1 V

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8.6.2.6 Driver Configuration Register (DRV8353F Only) (address = 0x07h)

The driver configuration register is shown in Figure 8-41 and described in Table 8-19.
Register access type: Read/Write
This register is only available with the DRV8353F devices.
Figure 8-41. Driver Configuration Register
10 9 8 7 6 5 4 3 2 1 0
CAL
Reserved
_MODE
R/W-000 0000 000b R/W-0b

Table 8-19. Driver Configuration Field Descriptions

Bit Field Type Default Description
10-1 Reserved R/W 000 0000 Reserved
000b
0 CAL_MODE R/W 0b 0b = Amplifier calibration operates in manual mode
1b = Amplifier calibration uses internal auto calibration routine

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

9.1 Application Information

The DRV835xF family of devices are primarily used in three-phase brushless DC motor control applications.
The design procedures in the Section 9.2 section highlight how to use and configure the DRV835xF family of
devices.
9.2 Typical Application
9.2.1 Primary Application
The DRV8353F is shown being used for a single supply, three-phase BLDC motor drive with individual half-
bridge current sense in this application example.

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1 …F 1 …F

40

39

36

35

32

31
38

37

34

33
VGLS

GND

DVDD

INLC

INHC

INLB

INHB

INLA

INHA

ENABLE
1 30
CPL nSCS
47 nF
2 29
CPH SCLK
VM VCC
3 28
VM SDI
1k VCC
0.1 …F
4 27
VDRAIN SDO
10 k
1 …F
5 26
VCP nFAULT
Thermal Pad
6 25
GHA GHA AGND
VCC
1 …F
7 24
SHA SHA VREF
8 23
GLA GLA SOC
9 22
SPA SPA SOB
10 21
SNA SNA GHC SOA
GHB

SHC

SNC
SNB

SHB

GLC

SPC
SPB

GLB
11

12

13

14

15

16

17

18

19

20
GHC
GHB

SHC

SNC
SHB
SNB

GLC

SPC
GLB
SPB

VM VM VM VM VM
CBULK CBYP CBYP CBYP CBULK

GHA GHB GHC

SHA SHB SHC

MOTA MOTB MOTC

GLA GLB GLC

SPA SPB SPC

RSENA RSENB RSENC

SNA SNB SNC

Figure 9-1. Primary Application Schematic

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9.2.1.1 Design Requirements

Table 9-1 lists the example input parameters for the system design.
Table 9-1. Design Parameters
EXAMPLE DESIGN PARAMETER REFERENCE EXAMPLE VALUE
Power supply voltage VVM, VVDRAIN, VVIN 48 V
MOSFET part number MOSFET CSD19535KCS
MOSFET total gate charge Qg 78 nC (typical) at VVGS = 10 V
MOSFET gate to drain charge Qgd 13 nC (typical)
Target output rise time tr 100 to 300 ns
Target output fall time tf 50 to 150 ns
PWM frequency ƒPWM 45 kHz
Maximum motor current Imax 100 A
ADC reference voltage VVREF 3.3 V
Winding sense current range ISENSE –40 A to +40 A
Motor RMS current IRMS 28.3 A
Sense resistor power rating PSENSE 3W
System ambient temperature TA –20°C to +60°C

9.2.1.2 Detailed Design Procedure

Table 9-2 lists the recommended values of the external components for the gate driver. Table 9-2 lists the
recommended values of the external components for the buck regulator.
Table 9-2. DRV835xF Gate-Driver External Components
COMPONENTS PIN 1 PIN 2 RECOMMENDED
CVM1 VM GND X5R or X7R, 0.1-µF, VM-rated capacitor
CVM2 VM GND ≥ 10 µF, VM-rated capacitor
CVCP VCP VM X5R or X7R, 1-µF, 16-V capacitor
CVGLS VGLS GND X5R or X7R, 1-µF, 16-V capacitor
CSW CPH CPL X5R or X7R, 47-nF, VDRAIN-rated capacitor
CDVDD DVDD DGND X5R or X7R, 1-µF, 6.3-V capacitor
RnFAULT VCC(1) nFAULT Pullup resistor
RSDO VCC(1) SDO Pullup resistor
RIDRIVE IDRIVE GND or DVDD DRV835xF hardware interface
RVDS VDS GND or DVDD DRV835xF hardware interface
RMODE MODE GND or DVDD DRV835xF hardware interface
RGAIN GAIN GND or DVDD DRV835xF hardware interface
CVREF VREF GND or DGND Optional capacitor rated for VREF
RASENSE SPA SNA and GND Sense shunt resistor
RBSENSE SPB SNB and GND Sense shunt resistor
RCSENSE SPC SNC and GND Sense shunt resistor

(1) VCC is not a pin on the DRV835xF family of devices, but a VCC supply voltage pullup is required for the open-drain output nFAULT
and SDO. These pins can also be pulled up to DVDD.

9.2.1.2.1 External MOSFET Support

The DRV835xF family of devices MOSFET support is based on the MOSFET gate charge, VCP charge-pump
capacity, VGLS regulator capacity, and output PWM switching frequency. For a quick calculation of MOSFET
driving capacity, use Equation 5 and Equation 6 for three phase BLDC motor applications.

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Trapezoidal 120° Commutation: IVCP/VGLS > Qg × ƒPWM (5)

Sinusoidal 180° Commutation: IVCP/VGLS > 3 × Qg × ƒPWM (6)

where
• ƒPWM is the maximum desired PWM switching frequency.
• Qg is the MOSFET total gate charge
• IVCP/VGLS is the charge pump or low-side regulator capacity, dependent on the VM pin voltage.
• The MOSFET multiplier based on the commutation control method, may vary based on implementation.
9.2.1.2.1.1 MOSFET Example
If a system is using VVM = 48 V (IVCP = 25 mA) and a maximum PWM switching frequency of 45 kHz, then the
VCP charge-pump and VGLS regulator can support MOSFETs using trapezoidal commutation with a Qg < 556
nC, and MOSFETs using sinusoidal commutation with a Qg < 185 nC.
9.2.1.2.2 IDRIVE Configuration
The gate drive current strength, IDRIVE, is selected based on the gate-to-drain charge of the external MOSFETs
and the target rise and fall times at the outputs. If IDRIVE is selected to be too low for a given MOSFET, then the
MOSFET may not turn on completely within the tDRIVE time and a gate drive fault may be asserted. Additionally,
slow rise and fall times will lead to higher switching power losses. TI recommends adjusting these values in
system with the required external MOSFETs and motor to determine the best possible setting for any application.
The IDRIVEP and IDRIVEN current for both the low-side and high-side MOSFETs are independently adjustable
on SPI devices through the SPI registers. On hardware interface devices, both source and sink settings are
selected at the same time on the IDRIVE pin.
For MOSFETs with a known gate-to-drain charge Qgd, desired rise time (tr), and a desired fall time (tf), use
Equation 7 and Equation 8 to calculate the value of IDRIVEP and IDRIVEN (respectively).

Qgd
IDRIVEP !
tr (7)

Qgd
IDRIVEN !
tf (8)

9.2.1.2.2.1 IDRIVE Example

Use Equation 9 and Equation 10 to calculate the value of IDRIVEP1 and IDRIVEP2 (respectively) for a gate to drain
charge of 13 nC and a rise time from 100 to 300 ns.

13 nC
IDRIVEP1 130 mA
100 ns (9)

13 nC
IDRIVEP2 43 mA
300 ns (10)

Select a value for IDRIVEP that is between 43 mA and 130 mA. For this example, the value of IDRIVEP was
selected as 100-mA source.
Use Equation 11 and Equation 12 to calculate the value of IDRIVEN1 and IDRIVEN2 (respectively) for a gate to drain
charge of 13 nC and a fall time from 50 to 150 ns.

13 nC
IDRIVEN1 260 mA
50 ns (11)

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13 nC
IDRIVEN2 87 mA
150 ns (12)

Select a value for IDRIVEN that is between 87 mA and 260 mA. For this example, the value of IDRIVEN was
selected as 200-mA sink.
9.2.1.2.3 VDS Overcurrent Monitor Configuration
The VDS monitors are configured based on the worst-case motor current and the RDS(on) of the external
MOSFETs as shown in Equation 13.

VDS _ OCP ! Imax u RDS(on)max (13)

9.2.1.2.3.1 VDS Overcurrent Example

The goal of this example is to set the VDS monitor to trip at a current greater than 75 A. According to the
CSD19535KCS 100 V N-Channel NexFET™ Power MOSFET data sheet, the RDS(on) value is 2.2 times higher
at 175°C, and the maximum RDS(on) value at a VGS of 10 V is 3.6 mΩ at TA = 25°C. From these values, the
approximate worst-case value of RDS(on) is 2.2 × 3.6 mΩ = 7.92 mΩ.
Using Equation 13 with a value of 7.92 mΩ for RDS(on) and a worst-case motor current of 75 A, Equation 14
shows the calculated desired value of the VDS overcurrent monitors.

VDS _ OCP ! 75 A u 7.92 m:

VDS _ OCP ! 0.594 V (14)

For this example, the value of VDS_OCP was selected as 0.6 V.

The SPI devices allow for adjustment of the deglitch time for the VDS overcurrent monitor. The deglitch time can
be set to 1 µs, 2 µs, 4 µs, or 8 µs.
9.2.1.2.4 Sense-Amplifier Bidirectional Configuration (DRV8353F)
The sense amplifier gain on the DRV8353F device and sense resistor value are selected based on the target
current range, VREF reference voltage, sense-resistor power rating, and operating temperature range. In
bidirectional operation of the sense amplifier, the dynamic range at the output is approximately calculated as
shown in Equation 15.

VVREF
VO VVREF 0.25 V
2 (15)

Use Equation 16 to calculate the approximate value of the selected sense resistor with VO calculated using
Equation 15.

VO
R PSENSE ! IRMS2 u R
AV u I (16)

From Equation 15 and Equation 16, select a target gain setting based on the power rating of the target sense
resistor.
9.2.1.2.4.1 Sense-Amplifier Example
In this system example, the value of VREF voltage is 3.3 V with a sense current from –40 to +40 A. The linear
range of the SOx output is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification). The differential range of the
sense amplifier input is –0.3 to +0.3 V (VDIFF).

3.3 V
VO 3.3 V 0.25 V 1.4 V
2 (17)

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1.4 V
R 2 W ! 28.32 u R o R 2.5 m:
A V u 40 A (18)

1.4 V
2.5 m: ! o A V ! 14
A V u 40 A (19)

Therefore, the gain setting must be selected as 20 V/V or 40 V/V and the value of the sense resistor must be
less than 2.5 mΩ to meet the power requirement for the sense resistor. For this example, the gain setting was
selected as 20 V/V. The value of the resistor and worst case current can be verified that R < 2.5 mΩ and Imax =
40 A does not violate the differential range specification of the sense amplifier input (VSPxD).
9.2.1.2.5 Single Supply Power Dissipation
Design care must be taken to make sure that the thermal ratings of the DRV835xF are not violated during
normal operation of the device. The is especially critical in higher voltage and higher ambient operation
applications where power dissipation or the device ambient temperature are increased.
To determine the temperature of the device in single supply operation, first the power internal power dissipation
must be calculated. The internal power dissipation has three primary components:
• VCP charge pump power dissipation (PVCP)
• VGLS low-side regulator power dissipation (PVGLS)
• VM device nominal power dissipation (PVM)
The values of PVCP and PVGLS can be approximated by referring to Section 9.2.1.2.1 to first determine IVCP and
IVGLS and then referring to Equation 20 and Equation 21.

PVCP = IVCP × (VVM + VVDRAIN) (20)

PVGLS = IVGLS × VVM (21)

The value of PVM can be calculated by referring to the data sheet parameter for IVM current and Equation 22.

PVM = IVM × VVM (22)

The total power dissipation is then calculated by summing the three components as shown in Equation 23.

Ptot = PVCP + PVGLS + PVM (23)

Lastly, the device junction temperature can be estimate by referring to Section 7.4 and Equation 24.

TJmax = TAmax + (RθJA × Ptot) (24)

The information in Section 7.4 is based off of a standardized test metric for package and PCB thermal
dissipation. The actual values may vary based on the actual PCB design used in the application.
9.2.1.2.6 Single Supply Power Dissipation Example
In this application example the device is configured for single supply operation. This configuration requires only
one power supply for the DRV835xF but comes at the tradeoff of increased internal power dissipation. The
junction temperature is estimated in the example below.
Use Equation 5 to calculate the value of IVCP and IVGLS for a MOSFET gate charge of 78 nC, all 3 high-side and
3 low-side MOSFETs switching, and a switching frequency of 45 kHz.

IVCP/VGLS = 78 nC × 3 × 45 kHz = 10.5 mA (25)

Use Equation 20, Equation 21, Equation 22, , and Equation 23 to calculate the value of Ptot for VVM = VVDRAIN =
VVIN = 48 V, IVM = 9.5 mA, IVCP = 10.5 mA, and IVGLS = 10.5 mA.

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PVCP = 10.5 mA × (48 V + 48 V) = 1 W (26)

PVGLS = 10.5 mA × 48 V = 0.5 W (27)

PVM = 9.5 mA × 48 V = 0.5 W (28)

Ptot = 1 W + 0.5 W + 0.5 W = 2.0 W (29)

Lastly, to estimate the device junction temperature during operation, use Equation 24 to calculate the value of
TJmax for TAmax = 60°C, RθJA = 26.1°C/W for the RTA package, and Ptot = 2.054 W. Again, please note that
the RθJA is highly dependent on the PCB design used in the actual application and should be verified. For more
information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics
application report.

TJmax = 60°C + (26.1°C/W × 2.0 W) = 112.2°C (30)

As shown in this example, the device is within its operational limits, but is operating almost to its maximum
operational junction temperature. Design care should be taken in the single supply configuration to correctly
manage the power dissipation of the device.
9.2.1.3 Application Curves

Figure 9-2. Gate Driver Operation 30% Duty Cycle Figure 9-3. Gate Driver Operation 90% Duty Cycle

Figure 9-4. IDRIVE Minimum Setting Positive Figure 9-5. IDRIVE Minimum Setting Negative
Current Current

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Figure 9-6. IDRIVE 300-mA and 600-mA Setting Figure 9-7. IDRIVE 300-mA and 600-mA Setting
Positive Current Negative Current

Figure 9-8. IDRIVE Maximum Setting Positive Figure 9-9. IDRIVE Maximum Setting Negative
Current Current

Figure 9-10. FOC Motor Commutation

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9.2.2 Alternative Application

In this application, the DRV8353F is configured to use one sense amplifier in unidirectional mode for a summing
current sense scheme often used in trapezoidal or hall-based BLDC commutation control. Additionally, the
device is configured in dual supply mode using an external buck regulator for the VM gate drive voltage supply to
decrease internal power dissipation.
VDRAIN VM
External External
VM VCC
DC/DC LDO
CIN COUT CIN COUT

1 …F 1 …F
40

39

36

35

32

31
38

37

34

33
VGLS

GND

DVDD

INLC

INHC

INLB

INHB

INLA

INHA

ENABLE
1 30
CPL nSCS
47 nF
2 29
CPH SCLK
VM VCC
3 28
VM SDI
VDRAIN 1k VCC
0.1 …F
4 27
VDRAIN SDO
10 k
1 …F
5 26
VCP nFAULT
Thermal Pad
6 25
GHA GHA AGND
VCC
1 …F
7 24
SHA SHA VREF
8 23
GLA GLA SOC
9 22
SPA SPA SOB
10 21
SNA SNA SOA
GHC
GHB

SHC

SNC
SNB

SHB

GLC

SPC
SPB

GLB
11

12

13

14

15

16

17

18

19

20
GHC
GHB

SHC
SHB
SNA

GLC

SNA
GLB

SPA
SPA

VDRAIN VDRAIN VDRAIN VDRAIN VDRAIN

CBULK CBYP CBYP CBYP CBULK

GHA GHB GHC

SHA SHB SHC

MOTA MOTB MOTC

GLA GLB GLC

SPA SPB SPC

RSEN

SNA

Figure 9-11. Alternative Application Schematic

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9.2.2.1 Design Requirements

Table 9-3 lists the example design input parameters for system design.
Table 9-3. Design Parameters
EXAMPLE DESIGN PARAMETER REFERENCE EXAMPLE VALUE
Power supply voltage VVM 12 V
MOSFET drain voltage VVDRAIN 48 V
MOSFET part number MOSFET CSD19535KCS
MOSFET total gate charge Qg 78 nC
PWM frequency fPWM 20 kHz
ADC reference voltage VVREF 3.3 V
Winding sense current range ISENSE 0 to 40 A
Motor RMS current IRMS 28.3 A
Sense-resistor power rating PSENSE 3W
System ambient temperature TA –20°C to +105°C

9.2.2.2 Detailed Design Procedure

9.2.2.2.1 Sense Amplifier Unidirectional Configuration
The sense amplifiers are configured to be unidirectional through the registers on SPI devices by writing a 0 to
the VREF_DIV bit.
The sense-amplifier gain and sense resistor values are selected based on the target current range, VREF,
sense-resistor power rating, and operating temperature range. In unidirectional operation of the sense amplifier,
use Equation 31 to calculate the approximate value of the dynamic range at the output.

VO VVREF 0.25 V 0.25 V VVREF 0.5 V (31)

Use Equation 32 to calculate the approximate value of the selected sense resistor.

VO
R PSENSE ! IRMS2 u R
AV u I (32)

where

• VO VVREF 0.5 V

From Equation 31 and Equation 32, select a target gain setting based on the power rating of a target sense
resistor.
9.2.2.2.1.1 Sense-Amplifier Example
In this system example, the value of VVREF is 3.3 V with a sense current from 0 to 40 A. The linear range of the
SOx output for the DRV8353x device is 0.25 V to VVREF – 0.25 V (from the VLINEAR specification). The differential
range of the sense-amplifier input is –0.3 to +0.3 V (VDIFF).

VO 3.3 V 0.5 V 2.8 V (33)

2.8 V
R 3 W ! 28.32 u R o R 3.75 m:
A V u 40 A (34)

2.8 V
3.75 m: ! o A V ! 18.7
A V u 40 A (35)

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Therefore, the gain setting must be selected as 20 V/V or 40 V/V and the value of the sense resistor must be
less than 3.75 mΩ to meet the power requirement for the sense resistor. For this example, the gain setting was
selected as 20 V/V. The value of the resistor and worst-case current can be verified that R < 3.75 mΩ and Imax =
40 A does not violate the differential range specification of the sense amplifier input (VSPxD).
9.2.2.2.1.2 Dual Supply Power Dissipation
Design care must be taken to make sure that the thermal ratings of the DRV835xF are not violated during
normal operation of the device. The is especially critical in higher voltage and higher ambient operation
applications where power dissipation or the device ambient temperature are increased.
To determine the temperature of the device in dual supply operation, first the internal power dissipation must be
calculated. The internal power dissipation has three primary components:
• VCP Charge pump power dissipation (PVCP)
• VGLS low-side regulator power dissipation (PVGLS)
• VM device nominal power dissipation (PVM)
The value of PVCP and PVGLS can be approximated by referring to Section 9.2.1.2.1 to first determine IVCP and
IVGLS and then referring to Equation 36 and Equation 37.

PVCP = IVCP × (VVM + VVDRAIN) (36)

PVGLS = IVGLS × VVM (37)

The value of PVM can be calculated by referring to the datasheet parameter for IVM current and Equation 38.

PVM = IVM × VVM (38)

The total power dissipation is then calculated by summing the four components as shown in Equation 39.

Ptot = PVCP + PVGLS + PVM (39)

Lastly, the device junction temperature can be estimate by referring to the Section 7.4 and Equation 40.

TJmax = TAmax + (RθJA × Ptot) (40)

Note that the information in the Section 7.4 is based off of a standardized test metric for package and PCB
thermal dissipation. The actual values may vary based on the actual PCB design used in the application.
9.2.2.2.1.3 Dual Supply Power Dissipation Example
In this application example the device is configured for dual supply operation. dual supply operation helps to
decrease the internal power dissipation by providing the gate driver with a lower supply voltage. This can be
derived from the internal buck regulator or an external power supply. The junction temperature is estimated in
the example below.
Use Equation 5 to calculate the value of IVCP and IVGLS for a MOSFET gate charge of 78 nC, 1 high-side and 1
low-side MOSFETs switch at a time, and a switching frequency of 20 kHz.

IVCP/VGLS = 78 nC × 1 × 20 kHz = 1.56 mA (41)

Use equation Equation 36, Equation 37, Equation 38, , and Equation 39 to calculate the value of Ptot for VVM =
12 V, VVDRAIN = 48 V, VVIN = 48 V, IVM = 9.5 mA, IVCP = 1.56 mA, and IVGLS = 1.56 mA.

PVCP = 1.56 mA × (12 V + 48 V) = 0.1 W (42)

PVGLS = 1.56 mA × 12 V = 0.02 W (43)

PVM = 9.5 mA × 12 V = 0.1 W (44)

Ptot = 0.1 W + 0.02 W + 0.1 W = 0.22 W (45)

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Lastly, to estimate the device junction temperature during operation, use Equation 40 to calculate the value of
TJmax for TAmax = 105°C, RθJA = 26.1°C/W for the RGZ package, and Ptot = 0.22 W. Again, note that the
RθJA is highly dependent on the PCB design used in the actual application and should be verified. For more
information about traditional and new thermal metrics, refer to the Semiconductor and IC Package Thermal
Metrics application report.

TJmax = 105°C + (26.1°C/W × 0.22 W) = 110.7°C (46)

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10 Power Supply Recommendations

The DRV835xF family of devices are designed to operate from an input voltage supply (VM) range between 9 V
and 75 V. A 0.1-µF ceramic capacitor rated for VM must be placed as near to the device as possible. In addition,
a bulk capacitor must be included on the VM pin but can be shared with the bulk bypass capacitance for the
external power MOSFETs. Additional bulk capacitance is required to bypass the external half-bridge MOSFETs
and should be sized according to the application requirements.
10.1 Bulk Capacitance Sizing
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is usually
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size. The
amount of local capacitance depends on a variety of factors including:
• The highest current required by the motor system
• The power supply's type, capacitance, and ability to source current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable supply voltage ripple
• Type of motor (brushed DC, brushless DC, stepper)
• The motor startup and braking methods
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands
or dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
stays stable and high current can be quickly supplied.
The data sheet provides a recommended minimum value, but system level testing is required to determine the
appropriate sized bulk capacitor.

Parasitic Wire
Inductance
Power Supply Motor Drive System

VM

+ +
Motor Driver
±

GND

Local IC Bypass
Bulk Capacitor Capacitor

Figure 10-1. Motor Drive Supply Parasitics Example

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11 Layout
11.1 Layout Guidelines
Bypass the VM pin to the GND pin using a low-ESR ceramic bypass capacitor with a recommended value of
0.1 µF. Place this capacitor as near to the VM pin as possible with a thick trace or ground plane connected
to the GND pin. Additionally, bypass the VM pin using a bulk capacitor rated for VM. This component can be
electrolytic. This capacitance must be at least 10 µF.
Additional bulk capacitance is required to bypass the high current path on the external MOSFETs. This bulk
capacitance should be placed such that it minimizes the length of any high current paths through the external
MOSFETs. The connecting metal traces should be as wide as possible, with numerous vias connecting PCB
layers. These practices minimize inductance and allow the bulk capacitor to deliver high current.
Place a low-ESR ceramic capacitor between the CPL and CPH pins. This capacitor should be 47 nF, rated for
VDRAIN, and be of type X5R or X7R. Additionally, place a low-ESR ceramic capacitor between the VCP and
VDRAIN pins and VGLS and GNDs. These capacitors should be 1 µF, rated for 16 V, and be of type X5R or
X7R.
Bypass the DVDD pin to the GND/DGND pin with a 1-µF low-ESR ceramic capacitor rated for 6.3 V and of type
X5R or X7R. Place this capacitor as near to the pin as possible and minimize the path from the capacitor to the
GND/DGND pin.
The VDRAIN pin can be shorted directly to the VM pin for single supply application configurations. However, if
a significant distance is between the device and the external MOSFETs, use a dedicated trace to connect to the
common point of the drains of the high-side external MOSFETs. Do not connect the SLx pins directly to GND.
Instead, use dedicated traces to connect these pins to the sources of the low-side external MOSFETs. These
recommendations allow for more accurate VDS sensing of the external MOSFETs for overcurrent detection.
Minimize the loop length for the high-side and low-side gate drivers. The high-side loop is from the GHx pin of
the device to the high-side power MOSFET gate, then follows the high-side MOSFET source back to the SHx
pin. The low-side loop is from the GLx pin of the device to the low-side power MOSFET gate, then follows the
low-side MOSFET source back to the SPx/SLx pins.

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11.2 Layout Example

S D

S D

S D

G D

OUTC
ENABLE

nFAULT D G

VREF
nSCS
SCLK
INHC

INHA
INHB
INLC

INLA
INLB

SOC
SDO

SOB
SOA
SDI

D S

D S
26 nFAULT

D S
25 AGND
24 VREF
30 nSCS
29 SCLK

27 SDO

21 SOC
22 SOB
23 SOA
28 SDI

ENABLE 31 20 SNC
INHA 32 19 SPC D G
INLA 33 18 GLC
INHB 34 17 SHC
INLB 35 16 GHC D S
Thermal Pad
INHC 36 15 GHB
INLC 37 14 SHB
D S
DVDD 38 13 GLB
GND 39 12 SPB
VGLS 40 13 SNB
11
D S

OUTB
10
1

8
4
2
3

9
5
6
7
CPL

VDRAIN
CPH
VM

SPA
VCP
GHA
SHA

SNA
GLA

S D

S D

S D

G D

S D

S D

S D

G D OUTA

D G

D S

D S

D S

Figure 11-1. Layout Example

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12 Device and Documentation Support

12.1 Device Support
12.1.1 Device Nomenclature
The following figure shows a legend for interpreting the complete device name:
DRV83 (5) (3) (F) (S) (RTA) (R)

Prefix Tape and Reel

DRV83 ± Three Phase Brushless DC R ± Tape and Reel
T ± Small Tape and Reel

Package
RTV ± 5 × 5 × 0.75 mm QFN
Series
RTA ± 6 x 6 × 0.75 mm QFN
5 ± 100 V device

Sense amplifiers Interface

0 ± No sense amplifiers S ± SPI interface
3 ± 3x sense amplifiers H ± Hardware interface

Buck Regulator
F ± Functional Safety Quality-Managed

12.2 Documentation Support

12.2.1 Related Documentation
For related documentation, refer to:
• Texas Instruments, DRV8353Rx-EVM User’s Guide user's guide
• Texas Instruments, DRV8353Rx-EVM GUI User’s Guide
• Texas Instruments, DRV8353Rx-EVM InstaSPIN™ Software Quick Start Guide
• Texas Instruments, DRV8350x-EVM User’s Guide user's guide
• Texas Instruments, DRV8350x-EVM GUI User’s Guide user's guide
• Texas Instruments, DRV8350x-EVM Sensorless Software User's Guide user's guide
• Texas Instruments, DRV8350x-EVM Sensored Software User's Guide user's guide
• Texas Instruments, CSD19535KCS 100 V N-Channel NexFET™ Power MOSFET data sheet
• Texas Instruments, Understanding IDRIVE and TDRIVE In TI Motor Gate Drivers application report
• Texas Instruments, Motor Drive Protection with TI Smart Gate Drive TI TechNote
• Texas Instruments, Reduce Motor Drive BOM and PCB Area with TI Smart Gate Drive TI TechNote
• Texas Instruments, Reducing EMI Radiated Emissions with TI Smart Gate Drive TI TechNote
• Texas Instruments, Hardware Design Considerations for an Efficient Vacuum Cleaner using BLDC Motor
• Texas Instruments, Hardware Design Considerations for an Electric Bicycle using BLDC Motor
• Texas Instruments, Industrial Motor Drive Solution Guide
• Texas Instruments, QFN/SON PCB Attachment application report
• Texas Instruments, Sensored 3-Phase BLDC Motor Control Using MSP430™ application report

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12.3 Related Links

The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to order now.
Table 12-1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER ORDER NOW
DOCUMENTS SOFTWARE COMMUNITY
DRV8350F Click here Click here Click here Click here Click here
DRV8353F Click here Click here Click here Click here Click here

12.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.5 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.6 Trademarks
NexFET™, InstaSPIN™, and MSP430™ are trademarks of Texas Instruments.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.7 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.8 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DRV8350FHRTVR ACTIVE WQFN RTV 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 8350FH

DRV8350FSRTVR ACTIVE WQFN RTV 32 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 8350FS

DRV8353FHRTAR ACTIVE WQFN RTA 40 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 8353FH

DRV8353FSRTAR ACTIVE WQFN RTA 40 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 8353FS

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 3-May-2021

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE OUTLINE
RTV0032E SCALE 3.000
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

5.15 B
A
4.85

PIN 1 INDEX AREA

5.15
4.85

SIDE WALL LEAD

METAL THICKNESS
0.8 DIM A
0.7 OPTION 1 OPTION 2
C 0.1 0.2

SEATING PLANE
0.05
0.00 0.08 C
2X 3.5 (DIM A) TYP
3.45 0.1 (0.2) TYP
9 16 EXPOSED
THERMAL PAD
28X 0.5
8
17

2X SYMM
33
3.5

0.30
32X
0.18
24 0.1 C A B
1
0.05 C
PIN 1 ID
(OPTIONAL) 32 25
SYMM
0.5
32X
0.3
4225196/A 08/2019

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RTV0032E WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 3.45)

SYMM
32 25
32X (0.6)

1 24

32X (0.24)

(1.475)
28X (0.5)

33 SYMM

(4.8)
( 0.2) TYP
VIA

8 17
(R0.05)
TYP

9 16
(1.475)

(4.8)

LAND PATTERN EXAMPLE

SCALE:18X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

SOLDER MASK METAL UNDER

OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4225196/A 08/2019

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RTV0032E WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.49)
(R0.05) TYP (0.845)
32 25
32X (0.6)

1 24

32X (0.24)

28X (0.5)
(0.845)
SYMM
33

(4.8)

8 17

METAL
TYP

9 16
SYMM

(4.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 33:

75% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4225196/A 08/2019

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
 PACKAGE OUTLINE
RTA0040B WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

6.1 A
B 5.9

PIN 1 INDEX AREA

6.1
5.9

0.8 MAX
C

SEATING PLANE
0.08 C
0.05
0.00 2X 4.5
4.15±0.1 (0.2) TYP
11 20
36X 0.5
10
21

41 SYMM
2X
4.5

1 30

PIN1 IDENTIFICATION 40X 0.28

0.16
(OPTIONAL) 40 31
SYMM 0.1 C A B
40X 0.5
0.3 0.05 C

4219112/A 07/2018

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RTA0040B WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK- NO LEAD
2X (5.8)
2X (4.5)
( 4.15)
40 31
40X (0.6)

40X (0.22)
1
30

36X (0.5)

SYMM 41 2X 2X
(4.5) (5.8)
2X
(0.685)

2X
(1.14)

(R0.05) TYP 10
21

12X (Ø0.2) VIA

TYP

11 20
2X (1.14) 2X (0.685)
SYMM

LAND PATTERN EXAMPLE

SCALE: 15X

0.07 MAX 0.07 MIN

ALL AROUND SOLDER MASK
ALL AROUND
OPENING

EXPOSED METAL EXPOSED METAL

METAL
SOLDER MASK METAL UNDER
OPENING SOLDER MASK
NON SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4219112/A 07/2018

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RTA0040B WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK- NO LEAD

2X (5.8)
2X (4.5)
9X ( 1.17)
40 31
40X (0.6)

40X (0.22)
1
41 30

36X (0.5)

SYMM 2X 2X
(4.5) (5.8)

2X
(1.37)

(R0.05) TYP 10
21

EXPOSED
METAL
11 20

2X (1.37)
SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD
71% PRINTED COVERAGE BY AREA
SCALE: 15X

4219112/A 07/2018

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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