DRV8803

SLVSAW5D – JULY 2011 – REVISED DECEMBER 2024

DRV8803 Quad Low-Side Driver IC

1 Features 3 Description
• 4-Channel Protected Low-Side Driver The DRV8803 provides a 4-channel low side driver
– Four NMOS FETs With Overcurrent Protection with overcurrent protection. The device has built-
– Integrated Inductive Clamp Diodes in diodes to clamp turnoff transients generated by
– Parallel Interface inductive loads and can be used to drive unipolar
• DW Package: 1.5A (Single Channel On) / stepper motors, DC motors, relays, solenoids, or other
800mA (Four Channels On) Maximum Drive loads.
Current per Channel (at 25°C) In the SOIC (DW) package, the DRV8803 can supply
• PWP Package: 2A (Single Channel On) / up to 1.5A (one channel on) or 800mA (all channels
1A (Four Channels On) Maximum Drive Current on) continuous output current per channel, at 25°C. In
per Channel (at 25°C, With Proper PCB the HTSSOP (PWP) package, the device can supply
Heatsinking) up to 2A (one channel on) or 1A (four channels on)
• DYZ Package: 1.9A (Single Channel On) / continuous output current per channel, at 25°C . In
0.9A (Four Channels On) Maximum Drive the SOT-23-THN (DYZ) package, the DRV8803 can
Current per Channel (at 25°C, With Proper PCB supply up to 1.9A (one channel on) or 900mA (all
Heatsinking) channels on) continuous output current per channel,
• 8.2V to 60V Operating Supply Voltage Range at 25°C with proper PCB heatsinking.
• Thermally Enhanced Surface Mount Package
The device is controlled through a simple parallel
2 Applications interface.
• Relay Drivers Internal shutdown functions are provided for
• Unipolar Stepper Motor Drivers over current protection, short circuit protection,
• Solenoid Drivers undervoltage lockout and overtemperature and faults
• General Low-Side Switch Applications are indicated by a fault output pin.
The DRV8803 is available in a 20-pin thermally-
enhanced SOIC package, 16-pin HTSSOP package
and 16-pin SOT-23-THN package (Eco-friendly: RoHS
& no Sb/Br).
Device Information (1)
PART PACKAGE BODY SIZE
PACKAGE
NUMBER SIZE(2) (NOM)
12.80mm × 12.80mm ×
DRV8803DW SOIC (20)
10.30mm 7.50mm
5.00mm × 5.00mm ×
DRV8803PWP HTSSOP (16)
6.40mm 4.40mm
SOT-23-THN 4.20mm × 4.20mm ×
DRV8803DYZ
(16) 2.00mm 2.00mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.
(2) The package size (length × width) is a nominal value and
includes pins, where applicable.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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VM VLOAD

ZOUT1

ZOUT2

ZOUT3

ZOUT4
VCLAMP
DRV8803
nFAULT Quad Low side
switches with
integrated Catch
Diodes
OUT1

OUT2
GPIO Interface
Controller

RESET OUT3
nENBL
OUT4
IN4 Fully protected
IN3
IN2
IN1
GND

Simplified Schematic

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Table of Contents
1 Features............................................................................1 7.1 Overview................................................................... 11
2 Applications..................................................................... 1 7.2 Functional Block Diagram......................................... 11
3 Description.......................................................................1 7.3 Feature Description...................................................11
4 Device Comparison......................................................... 4 7.4 Device Functional Modes..........................................12
5 Pin Configuration and Functions...................................4 8 Application and Implementation.................................. 13
Pin Functions.................................................................... 4 8.1 Application Information............................................. 13
6 Specification.................................................................... 6 8.2 Layout....................................................................... 18
6.1 Absolute Maximum Ratings........................................ 6 9 Device and Documentation Support............................21
6.2 ESD Ratings............................................................... 6 9.1 Documentation Support............................................ 21
6.3 Recommended Operating Conditions.........................6 9.2 Community Resources..............................................21
6.4 Thermal Information....................................................6 9.3 Trademarks............................................................... 21
6.5 Electrical Characteristics.............................................7 10 Revision History.......................................................... 21
6.6 Timing Requirements.................................................. 9 11 Mechanical, Packaging, and Orderable
6.7 Typical Characteristics.............................................. 10 Information.................................................................... 21
7 Detailed Description...................................................... 11

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4 Device Comparison
Following is the Summary of the RON and package offerings for DRV8803
Part number LS RON(TYP) Package Body Size (nominal)

SOIC (20) 12.80mm x 7.50mm

500mΩ
DRV8803 HTSSOP (16) 5.00mm × 4.40mm

400mΩ SOT-23-THN (16) 4.20mm × 2mm

5 Pin Configuration and Functions

VM 1 20 nFAULT
VCLAMP 2 19 NC
OUT1 3 18 IN1
OUT2 4 17 IN2
GND 5 16 GND
GND 6 15 GND
GND 7 14 GND
OUT3 8 13 IN3
OUT4 9 12 IN4
nENBL 10 11 RESET

Figure 5-1. DW Package 20-Pin SOIC Top View

VM 1 16 nFAULT
VCLAMP 2 15 NC
OUT1 3 14 IN1
OUT2 4 13 IN2
GND
GND 5 12 GND
OUT3 6 11 IN3
OUT4 7 10 IN4
nENBL 8 9 RESET

Figure 5-2. PWP Package 16-Pin HTSSOP Top View

VM 1 16 nFAULT
VCLAMP 2 15 NC
OUT1 3 14 IN1
OUT2 4 13 IN2
GND
GND 5 12 GND
OUT3 6 11 IN3
OUT4 7 10 IN4
nENBL 8 9 RESET

Figure 5-3. DYZ Package 16-Pin SOT-23-THN Top View

Pin Functions
PIN
EXTERNAL COMPONENTS
SOT-23- I/O(1) DESCRIPTION
NAME SOIC HTSSOP OR CONNECTIONS
THN
POWER AND GROUND

5, 6, 7, 5, 12, 5,12,
GND — Device ground All pins must be connected to GND.
14, 15, 16 PPAD PPAD

VM 1 1 1 — Device power supply Connect to motor supply (8.2V - 60V).

CONTROL
Active low enables outputs – internal
nENBL 10 8 8 I Enable input
pulldown

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PIN
EXTERNAL COMPONENTS
SOT-23- I/O(1) DESCRIPTION
NAME SOIC HTSSOP OR CONNECTIONS
THN
Active high resets internal logic and OCP
RESET 11 9 9 I Reset input
– internal pulldown
IN1 = 1 drives OUT1 low – internal
IN1 18 14 14 I Channel 1 input
pulldown
IN2 = 1 drives OUT2 low – internal
IN2 17 13 13 I Channel 2input
pulldown
IN3 = 1 drives OUT3 low – internal
IN3 13 11 11 I Channel 3 input
pulldown
IN4 = 1 drives OUT4 low – internal
IN4 12 10 10 I Channel 4 input
pulldown
STATUS
Logic low when in fault condition
nFAULT 20 16 16 OD Fault
(overtemperature, overcurrent)
OUTPUT
OUT1 3 3 3 O Output 1 Connect to load 1

OUT2 4 4 4 O Output 2 Connect to load 2

OUT3 8 6 6 O Output 3 Connect to load 3

OUT4 9 7 7 O Output 4 Connect to load 4

Connect to VM supply, or zener diode to
VCLAMP 2 2 2 — Output clamp voltage
VM supply

(1) Directions: I = input, O = output, OD = open-drain output

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6 Specification
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VM Power supply voltage –0.3 65 V
VOUTx Output voltage –0.3 65 V
VCLAMP Clamp voltage –0.3 65 V
nFAULT Output current 20 mA
Peak clamp diode current 2 A
DC or RMS clamp diode current 1 A
Digital input pin voltage –0.5 7 V
nFAULT Digital output pin voltage –0.5 7 V
Peak motor drive output current, t < 1 μS Internally limited A
Continuous total power dissipation See Thermal Information
TJ Operating virtual junction temperature –40 150 °C
Tstg Storage temperature –60 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
6.2 ESD Ratings
VALUE UNIT

Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±3000
V(ESD) V
discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±1000

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN NOM MAX UNIT
VM Power supply voltage 8.2 60 V
VCLAMP Output clamp voltage(2) 0 60 V
Single channel on 1.5
SOIC package(1), TA = 25°C
Four channels on 0.8
Single channel on 2
IOUT Continuous output current HTSSOP package(1), TA = 25°C A
Four channels on 1
Single channel on 1.9
DYZ package(1), TA = 25°C
Four channels on 0.9

(1) Power dissipation and thermal limits must be observed.

(2) VCLAMP is used only to supply the clamp diodes. It is not a power supply input.

6.4 Thermal Information

DRV8803

PWP DYZ
THERMAL METRIC(1) DW (SOIC) UNIT
(HTSSOP) (SOT -23 THN

20 PINS 16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 67.7 39.6 53.2 °C/W

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DRV8803

PWP DYZ
THERMAL METRIC(1) DW (SOIC) UNIT
(HTSSOP) (SOT -23 THN

20 PINS 16 PINS 16 PINS

RθJC(top) Junction-to-case (top) thermal resistance 32.9 24.6 76.8 °C/W

RθJB Junction-to-board thermal resistance 35.4 20.3 22.2 °C/W

ψJT Junction-to-top characterization parameter 8.2 0.7 8.2 °C/W

ψJB Junction-to-board characterization parameter 34.9 20.1 22.2 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 2.3 9.6 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.5 Electrical Characteristics

TA = 25°C, over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLIES
IVM VM operating supply current VM = 24 V 1.6 2.1 mA
VUVLO VM undervoltage lockout voltage VM rising 8.2 V
LOGIC-LEVEL INPUTS (SCHMITT TRIGGER INPUTS WITH HYSTERESIS)
VIL Input low voltage 0.6 0.7 V
VIH Input high voltage 2 V
VHYS Input hysteresis 0.45 V
IIL Input low current VIN = 0 –20 20 μA
IIH Input high current VIN = 3.3 V 100 μA
RPD Pulldown resistance 100 kΩ
nFAULT OUTPUT (OPEN-DRAIN OUTPUT)
VOL Output low voltage IO = 5 mA 0.5 V
IOH Output high leakage current VO = 3.3 V 1 μA
LOW-SIDE FETS
FET on resistance, VM = 24 V, IO = 700 mA, TJ = 25°C 0.5
Ω
HTSSOP and SOIC package VM = 24 V, IO = 700 mA, TJ = 85°C 0.75 0.8
RON
FET on resistance, SOT-23-THN VM = 24 V, IO = 700 mA, TJ = 25°C 0.4
Ω
package VM = 24 V, IO = 700 mA, TJ = 85°C 0.64
IOFF Off-state leakage current –50 50 μA
HIGH-SIDE DIODES
VF Diode forward voltage VM = 24 V, IO = 700 mA, TJ = 25°C 1.2 V
IOFF Off-state leakage current VM = 24 V, TJ = 25°C –50 50 μA
OUTPUTS
tR Rise time VM = 24 V, IO = 700 mA, Resistive load 50 300 ns
tF Fall time VM = 24 V, IO = 700 mA, Resistive load 50 300 ns
PROTECTION CIRCUITS
IOCP Overcurrent protection trip level 2.3 3.8 A
Overcurrent protection deglitch
tOCP 3.5 µs
time
tRETRY Overcurrent protection retry time 1.2 ms

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TA = 25°C, over recommended operating conditions (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tTSD Thermal shutdown temperature Die temperature(1) 150 160 180 °C

(1) Not production tested.

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6.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
1 tOE(ENABLE) Enable time, nENBL to output low 50 ns
2 tPD(L-H) Propagation delay time, INx to OUTx, low to high 800 ns
3 tPD(H-L) Propagation delay time, INx to OUTx, high to low 800 ns
— tRESET RESET pulse width 20 µs

(1) Not production tested.

nENBL

INx

OUTx

1 2 3

Figure 6-1. DRV8803 Timing Requirements

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6.7 Typical Characteristics

1.80 1.80
1.75 1.75
1.70 1.70

Supply Current (mA)

Supply Current (mA)

1.65 1.65
1.60 1.60
1.55 1.55
1.50 1.50
1.45 1.45
1.40 8V 24 V 1.40
-40° C 25° C
1.35 1.35
30 V 60 V 75° C 125° C
1.30 1.30
-40° C 25° C 75° C 125° C 8V 24 V 30 V 60 V
Temperature (ƒC) C001 Supply Voltage (V) C002

Figure 6-2. Supply Current Over Temperature Figure 6-3. Supply Current Over VM
900 1000
-40° C 25° C
900 75° C 125° C
800
800
700
Rdson (mŸ)
Rdson (mŸ)

700

600 600

500
500
400
400 8V
300
60 V
300 200
-40° C 25° C 75° C 125° C 8V 60 V
Temperature (ƒC) C005 Supply Voltage (V) C006

Figure 6-4. RDS(on) Over Temperature Figure 6-5. RDS(on) Over VM

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7 Detailed Description
7.1 Overview
The DRV8803 device is an integrated 4-channel low side driver solution for any low side switch application.
The integrated overcurrent protection limits the motor current to a fixed maximum. Four logic inputs control the
low-side driver outputs which consist of four N-channel MOSFETs that have a typical RDS(on) of 500mΩ (PWP
and DW package) and 400 mΩ (DYZ Package). A single power input VM serves as the device power and is
internally regulated to power the internal low side gate drive. Motor speed can be controlled with pulse-width
modulation from 0kHz to 100kHz. The device outputs can be disabled by bringing nENBL pin high. The thermal
shutdown protection lets the device automatically shut down if the die temperature exceeds a TTSD limit. UVLO
protection will disable all circuitry in the device if VM drops below the undervoltage lockout threshold.
7.2 Functional Block Diagram
8.2V – 60V
8.2V – 60V
Internal Int. VCC Optional
VM Reference Zener
Regs LS Gate
UVLO Drive
VCLAMP

nENBL
OCP OUT1
& Inductive
RESET Gate Load
Drive

IN1
OUT2
OCP
IN2 & Inductive
Gate Load
Drive
IN3 Control
Logic

IN4 OCP OUT3

& Inductive
Gate Load
nFAULT Drive

OCP OUT4
Thermal & Inductive
Shut down Gate Load
Drive

GND
(multiple pins)

7.3 Feature Description

7.3.1 Output Drivers
The DRV8803 device contains four protected low-side drivers. Each output has an integrated clamp diode
connected to a common pin, VCLAMP.
VCLAMP can be connected to the main power supply voltage, VM. VCLAMP can also be connected to a Zener
or TVS diode to VM, allowing the switch voltage to exceed the main supply voltage VM. This connection can be
beneficial when driving loads that require very fast current decay, such as unipolar stepper motors.
In all cases, the voltage on the outputs must not be allowed to exceed the maximum output voltage specification.
7.3.2 Protection Circuits
The DRV8803 device is fully protected against undervoltage, overcurrent and overtemperature events.

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7.3.2.1 Overcurrent Protection (OCP)

An analog current limit circuit on each FET limits the current through the FET by removing the gate drive. If
this analog current limit persists for longer than the tOCP deglitch time (approximately 3.5µs), the driver will
be disabled and the nFAULT pin will be driven low. The driver will remain disabled for the tRETRY retry time
(approximately 1.2ms), then the fault will be automatically cleared. The fault will be cleared immediately if either
the RESET pin is activated or the VM is removed and reapplied.
7.3.2.2 Thermal Shutdown (TSD)
If the die temperature exceeds safe limits, all output FETs will be disabled and the nFAULT pin will be driven low.
Once the die temperature has fallen to a safe level, operation will automatically resume.
7.3.2.3 Undervoltage Lockout (UVLO)
If at any time the voltage on the VM pin falls below the undervoltage lockout threshold voltage, all circuitry in the
device will be disabled, and internal logic will be reset. Operation will resume when VM rises above the UVLO
threshold.
7.4 Device Functional Modes
7.4.1 Parallel Interface Operation
The DRV8803 device is controlled with a simple parallel interface. Logically, the interface is shown in Figure 7-1.

nENBL OUT1

IN1
OUT2

IN2
OUT3

IN3
OUT4

IN4

Figure 7-1. Parallel Interface Operation

7.4.2 nENBL and RESET Operation

The nENBL pin enables or disables the output drivers. nENBL must be low to enable the outputs. Note that
nENBL has an internal pulldown.
The RESET pin, when driven active high, resets internal logic. All inputs are ignored while RESET is active. Note
that RESET has an internal pulldown. An internal power-up reset is also provided, so it is not required to drive
RESET at power up.

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and
TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.

8.1 Application Information

The DRV8803 device can be used to drive upto four independent unipolar loads such as unipolar BDCs,
solenoids such as valves, relays etc. or to drive one unipolar stepper
8.1.1 Application as Load driver
VLOAD

VM

0.1 μF 100 μF
DRV8803
1 VM nFAULT 16

2 VCLAMP NC 15

3 OUT1 IN1 14

4 OUT2 IN2 13

5 GND GND 12

6 OUT3 IN3 11

7 OUT4 IN4 10

8 nENBL RESET 9

Figure 8-1. DRV8803 used to drive 4 Independent solenoid valves

8.1.1.1 Design Requirements

Table 8-1 lists the design parameters for this design example.
Table 8-1. Design Parameters
DESIGN PARAMETER REFERENCE EXAMPLE VALUE
Supply Voltage VM, VLOAD 24V

Valve Peak current IPEAK 200mA

Valve Peak current time tPEAK 100ms

Valve Hold current IHOLD 100mA

PWM frequency fPWM 25kHz

8.1.1.2 Detailed Design Procedure

8.1.1.2.1 Supply Voltage
This is characteristic to the loads used. A higher voltage allows for fast opening/closing of the solenoid, enabling
faster operation.

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8.1.1.2.2 Load Current

The current path starts from the supply VLOAD, and moves through the inductive winding load, and low-side
sinking NMOS power FET. Power dissipation losses in one sink NMOS power FET are shown in Equation 1.

P = I2 × RDS(on) (1)

The DRV8803 device has been measured to be capable of 1.5A Single Channel or 800-mA Four Channels with
the DW package, 2A Single Channel or 1A Four Channels with the PWP, and 1.9A Single Channel or 0.9A Four
Channels with the DYZ package at 25°C on standard FR-4 PCBs. The maximum RMS current varies based on
PCB design and the ambient temperature.
With loads such as Relays and solenoid valves, the load tends to heat up and degrade if it is allowed to remain
completely turned on. This can affect the long term reliability of the load and can even damage it in some cases.
The DRV8803 offers an integrated Free wheeling diode and a simple-to-use parallel interface. Since such loads
are inductive, the user can PWM the LSFET ON/OFF to regulate the current.
8.1.1.2.2.1 Peak Current
Load such as Solenoid/Relay needs to be energized at a temporary higher level of Load current and his higher
level of current needs to be maintained for as long as Peak time (tPEAK) in order for the load to reliably turn on.
This Load current can be controlled by PWM control of the LSFET at required duty cycle.
8.1.1.2.2.2 Hold Current
Once the Peak time is elapsed, the Duty cycle and consequently Load current can be lowered to a Holding value
of current. The Load can be kept on at this lower current for much longer durations
8.1.1.2.2.3 Frequency
The LSFET can be PWM controlled at a frequency which can be decided based on factors such as Load
Inductance, Load resistance, desired/ tolerable ripply in Load current. PWM can be done outside audio band
(>20kHz) for low audible noise operation

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8.1.1.3 Application Curves

Figure 8-2. DRV8803 used to drive Solenoid Valves

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8.1.2 Application as Unipolar Stepper Driver

Figure 8-3. DRV8803 used to drive one 5-wire unipolar stepper

8.1.2.1 Design Requirements

Following Table lists the Design parameters for this design example
Table 8-2. Design Parameters
DESIGN PARAMETER REFERENCE EXAMPLE VALUE

Supply Voltage VM 24V

Motor Winding Resistance RL 7.4Ω / phase

Motor Full step Angle θSTEP 1.8° /step

Motor Rated Current IRATED 0.75A

PWM frequency fPWM 31.25kHz

8.1.2.2 Detailed Design Procedure

8.1.2.2.1 Motor Voltage
The motor voltage to use will depend on the ratings of the motor selected and the desired torque. A higher
voltage shortens the current rise time in the coils of the stepper motor allowing the motor to produce a greater
average torque. Using a higher voltage also allows the motor to operate at a faster speed than a lower voltage.
8.1.2.2.2 Drive Current
The current path starts from the supply VM, and moves through the inductive winding load, and low-side sinking
NMOS power FET. Power dissipation losses in one sink NMOS power FET are shown in Equation 1.

P = I2 × RDS(on) (2)

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The DRV8803 device has been measured to be capable of 1.5A Single Channel or 800-mA Four Channels with
the DW package, 2A Single Channel or 1A Four Channels with the PWP, and 1.9A Single Channel or 0.9A Four
Channels with the DYZ package at 25°C on standard FR-4 PCBs. The maximum RMS current varies based on
PCB design and the ambient temperature.
8.1.2.3 Application Curves

Figure 8-4. Current Ramp With a 16Ω, 1mH RL Figure 8-5. Current Ramp With a 16Ω, 1mH RL
Load and VM = 8.2V Load and VM = 30V

Figure 8-6. OCP With VM = 8.2V and OUT1 Shorted Figure 8-7. OCP Separated by tRETRY With VM =
to VM 8.2V and OUT1 Shorted to VM

Power Supply Recommendations

8.1 Bulk Capacitance
Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system.
• The power supply’s capacitance and ability to source current.
• The amount of parasitic inductance between the power supply and motor system.
• The acceptable voltage ripple.
• The type of motor used (Brushed DC, Brushless DC, Stepper).

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• The motor braking method.

The inductance between the power supply and the motor drive system will limit the rate of current that can
change from the power supply. If the local bulk capacitance is too small, the system will respond to excessive
current demands or dumps from the motor with a change in voltage. When adequate bulk capacitance is used,
the motor voltage remains stable, and a high current can be quickly supplied.
Parasitic Wire
Inductance
Power Supply Motor Drive System

VM

+ + Motor
– Driver

GND

Local IC Bypass
Bulk Capacitor Capacitor

Example Setup of Motor Drive System with External Power Supply

Figure 8-8. Example Setup of Motor Drive System With External Power Supply

The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.
8.2 Layout
8.2.1 Layout Guidelines
The bulk capacitor should be placed to minimize the distance of the high-current path through the motor driver
device. The connecting metal trace widths should be as wide as possible, and numerous vias should be used
when connecting PCB layers. These practices minimize inductance and allow the bulk capacitor to deliver high
current.
Small-value capacitors should be ceramic, and placed closely to device pins.
The high-current device outputs should use wide metal traces.
The device thermal pad should be soldered to the PCB top-layer ground plane. Multiple vias should be used to
connect to a large bottom-layer ground plane. The use of large metal planes and multiple vias help dissipate the
I2 × RDS(on) heat that is generated in the device.

18 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8803

 DRV8803
www.ti.com SLVSAW5D – JULY 2011 – REVISED DECEMBER 2024

8.2.2 Layout Example

Figure 8-9. Recommended Layout

8.2.3 Thermal Consideration

8.2.3.1 Thermal Protection
The DRV8803 device has thermal shutdown (TSD) as described above. If the die temperature exceeds
approximately 150°C, the device will be disabled until the temperature drops to a safe level.
Any tendency of the device to enter TSD is an indication of either excessive power dissipation, insufficient
heatsinking, or too high an ambient temperature.
8.2.3.2 Power Dissipation
Power dissipation in the DRV8803 device is dominated by the power dissipated in the output FET resistance,
or RDS(on). Average power dissipation of each FET when running a static load can be roughly estimated by
Equation 3:

P = RDS(ON) · (IOUT)2 (3)

where
• P is the power dissipation of one FET
• RDS(ON) is the resistance of each FET
• IOUT is equal to the average current drawn by the load.
At start-up and fault conditions, this current is much higher than normal running current; consider these peak
currents and their duration. When driving more than one load simultaneously, the power in all active output
stages must be summed.
The maximum amount of power that can be dissipated in the device is dependent on ambient temperature and
heatsinking.
Note that R DS(on) increases with temperature, so as the device heats, the power dissipation increases. This must
be taken into consideration when sizing the heatsink.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19

Product Folder Links: DRV8803
DRV8803
SLVSAW5D – JULY 2011 – REVISED DECEMBER 2024 www.ti.com

8.2.3.3 Heatsinking
The DRV8803DW package uses a standard SOIC outline, but has the center pins internally fused to the die
pad to more efficiently remove heat from the device. The two center leads on each side of the package should
be connected together to as large a copper area on the PCB as is possible to remove heat from the device. If
the copper area is on the opposite side of the PCB from the device, thermal vias are used to transfer the heat
between top and bottom layers.
In general, the more copper area that can be provided, the more power can be dissipated.
The DRV8803PWP (HTSSOP package) and the DRV8803DYZ (SOT-23-THN package) uses an exposed
thermal pad. The exposed pad removes heat from the device. For proper operation, this pad must be thermally
connected to copper on the PCB to dissipate heat. On a multi-layer PCB with a ground plane, this can be
accomplished by adding a number of vias to connect the thermal pad to the ground plane. On PCBs without
internal planes, copper area can be added on either side of the PCB to dissipate heat. If the copper area is on
the opposite side of the PCB from the device, thermal vias are used to transfer the heat between top and bottom
layers.
For details about how to design the PCB, see the TI Application Report, PowerPAD Thermally Enhanced
Package (SLMA002), and TI Application Brief, PowerPAD Made Easy (SLMA004), available at www.ti.com.

20 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8803

 DRV8803
www.ti.com SLVSAW5D – JULY 2011 – REVISED DECEMBER 2024

9 Device and Documentation Support

9.1 Documentation Support
9.1.1 Related Documentation
For related documentation see the following:
• PowerPAD Thermally Enhanced Package, SLMA002.
• PowerPAD Made Easy, SLMA004.
9.2 Community Resources
9.3 Trademarks
All trademarks are the property of their respective owners.

10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (November 2015) to Revision D (July 2024) Page
• Added DYZ package drawing, thermal information, Updated Electrical characteristics to include DYZ
Package Rdson.................................................................................................................................................. 1
• Added DYZ Package current capability..............................................................................................................6

Changes from Revision B (February 2012) to Revision C (November 2015) Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1
• Changed Continuous output current, single channel on, TA = 25°C, HTSSOP package MAX value from 1.5A
to 2A................................................................................................................................................................... 7
• Changed Continuous output current, four channels on, TA = 25°C, HTSSOP package MAX value from 0.8A
to 1A................................................................................................................................................................... 7

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 21

Product Folder Links: DRV8803
DRV8803
SLVSAW5D – JULY 2011 – REVISED DECEMBER 2024 www.ti.com

22 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8803

 DRV8803
www.ti.com SLVSAW5D – JULY 2011 – REVISED DECEMBER 2024

Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 23

Product Folder Links: DRV8803
DRV8803
SLVSAW5D – JULY 2011 – REVISED DECEMBER 2024 www.ti.com

24 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated

Product Folder Links: DRV8803

 PACKAGE OPTION ADDENDUM

www.ti.com 25-Dec-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DRV8803DW LIFEBUY SOIC DW 20 25 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 DRV8803DW
DRV8803DWR ACTIVE SOIC DW 20 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 DRV8803DW Samples

DRV8803DYZR ACTIVE SOT-23-THIN DYZ 16 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 DRV8803 Samples

DRV8803PWP LIFEBUY HTSSOP PWP 16 90 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 DRV8803
DRV8803PWPR ACTIVE HTSSOP PWP 16 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 125 DRV8803 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 25-Dec-2024

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8803DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
DRV8803PWPR HTSSOP PWP 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV8803DWR SOIC DW 20 2000 367.0 367.0 45.0
DRV8803PWPR HTSSOP PWP 16 2000 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
DRV8803DW DW SOIC 20 25 507 12.83 5080 6.6
DRV8803PWP PWP HTSSOP 16 90 530 10.2 3600 3.5

Pack Materials-Page 3
 PACKAGE OUTLINE
PWP0016J SCALE 2.500
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

6.6 C SEATING
TYP PLANE
6.2
A 0.1 C
PIN 1 INDEX
AREA
14X 0.65
16
1

2X
5.1
4.55
4.9
NOTE 3

8
9
4.5 0.30
B 16X
4.3 0.19
0.1 C A B

(0.15) TYP

SEE DETAIL A

8 9

0.25
3.55 GAGE PLANE 1.2 MAX
2.68

0.75 0.15
0 -8 0.50 0.05
1 16 DETAIL A
A 20

TYPICAL
2.46 THERMAL
1.75 PAD

4223595/A 03/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.

www.ti.com
 EXAMPLE BOARD LAYOUT
PWP0016J TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(3.4)
NOTE 8 METAL COVERED
(2.46) BY SOLDER MASK
16X (1.5)
SYMM SEE DETAILS

16X (0.45) 1 16

(1.3) TYP
(R0.05) TYP

SYMM (0.65)
(3.55) (5)
NOTE 8
14X (0.65)

( 0.2) TYP
VIA 8 9

SOLDER MASK (1.35) TYP

DEFINED PAD
(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
15.000

4223595/A 03/2017
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
8. Size of metal pad may vary due to creepage requirement.
9. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
PWP0016J TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(2.46)
16X (1.5) BASED ON METAL COVERED
0.125 THICK BY SOLDER MASK
STENCIL

16X (0.45) 1 16

(R0.05) TYP

SYMM (3.55)
BASED ON
0.125 THICK
STENCIL
14X (0.65)

8 9

SYMM SEE TABLE FOR

DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.8) THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.75 X 3.97
0.125 2.46 X 3.55 (SHOWN)
0.15 2.25 X 3.24
0.175 2.08 X 3.00

4223595/A 03/2017
NOTES: (continued)

10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DYZ0016A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

SEATING PLANE

3.37 C
3.17

A PIN 1 INDEX 0.1 C

AREA
14X 0.5

1 16 16 1

4.3 2X
4.1 2.9
NOTE 3 3.5 2.7

8 9 8
9

1.2
B 2.1 1
1.9 1.1 MAX

16X 0.31
0.11
(9°) TYP
0.1 C A B

0.2 TYP
0.08

SEE DETAIL A

0.25
GAUGE PLANE
8°
0°

0.63 0.1
0.33 0.0
DETAIL A
TYP

4228945/C 03/2024

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
5. Reference JEDEC Registration MO-345, Variation AA

www.ti.com
 EXAMPLE BOARD LAYOUT
DYZ0016A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

(1.55)
(1.1)

SYMM

16X (1.05)

1 16

16X (0.3)

(R0.05) TYP

SYMM
14X (0.5) (4.2)
(0.5) (2.8)

(1) TYP

9
8

(0.85) TYP

(3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X

SOLDER MASK METAL UNDER

OPENING SOLDER MASK SOLDER MASK
METAL OPENING

NON- SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4228945/C 03/2024

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DYZ0016A SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE

(1.1)

SYMM
16X (1.05)

1 16

16X (0.3)

(R0.05) TYP

SYMM
(2.8)

14X (0.5)

9
8

(3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 20X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 1.23 X 3.13
0.125 1.10 X 2.80 (SHOWN)
0.15 1.00 X 2.56
0.175 0.93 X 2.37

4228945/C 03/2024

NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

www.ti.com
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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