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Dual Full Bridge PWM Motor Driver

Check for Samples: DRV8402

1FEATURES The DRV8402 can operate at up to 500 kHz

switching frequency while still maintaining precise
• High-Efficiency Power Stage (up to 96%) with control and high efficiency. It also has an innovative
Low RDS(on) MOSFETs (80 mΩ at TJ = 25°C) protection system integrated on-chip, safeguarding
• Operating Supply Voltage up to 50 V the device against a wide range of fault conditions
(65 V Absolute Maximum) that could damage the system. These safeguards are
• 10 A Continuous Output Current and 24 A short-circuit protection, overcurrent protection,
undervoltage protection, and two-stage thermal
Peak Current per Device
protection. The DRV8402 has a current-limiting circuit
• PWM Operating Frequency up to 500 kHz that prevents device shutdown during load transients
• Integrated Self-Protection Circuits such as motor start-up. A programmable overcurrent
• Programmable Cycle-by-Cycle Current Limit detector allows adjustable current limit and protection
level to meet different motor requirements.
Protection
• Independent Supply and Ground Pins for Each The DRV8402 has unique independent supply and
Half Bridge ground pins for each half bridge, which makes it
possible to provide current measurement through
• Intelligent Gate Drive and Cross Conduction external shunt resistor and support multiple motors
Prevention with different power supply voltage requirements.
• No External Snubber or Schottky Diode is
Required Simplified Application Diagram
• Thermally Enhanced DKD (36-pin PSOP3)
Package

APPLICATIONS
• Brushed DC, Brushless DC, and Stepper
Motors
• Three Phase Permanent Magnet Synchronous
Motors
• Robotic and Haptic Control System
• Actuators and Pumps
• Precision Instruments
• TEC Drivers

DESCRIPTION
The DRV8402 is a high performance, integrated dual
full bridge motor driver with an advanced protection
system. Because of the low RDS(on) and intelligent
gate drive design, the efficiency of this motor driver
can be up to 96%, which enables the use of smaller
power supplies and heatsinks, and is a good
candidate for energy efficient applications. This
device requires two power supplies, one at 12V for
GVDD and VDD, and one up to 50V for PVDD. The
DRV8402 is capable of driving 5 A continuous RMS
current and 12 A peak current per full bridge with low
idle power dissipation. It can also be used for up to
10 A continuous current and 24 A peak current in
parallel full bridge operation.
1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2009, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS

(1)
Over operating free-air temperature range unless otherwise noted
PARAMETER VALUE
VDD to AGND –0.3 V to 13.2 V
GVDD_X to AGND –0.3 V to 13.2 V
(2)
PVDD_X to GND_X –0.3 V to 65 V
(2)
OUT_X to GND_X –0.3 V to 65V
(2)
BST_X to GND_X –0.3 V to 75 V
Transient peak output current (per pin), pulse width limited by internal over-current 15 A
protection circuit.
VREG to AGND –0.3 V to 4.2 V
GND_X to GND –0.3 V to 0.3 V
GND_X to AGND –0.3 V to 0.3 V
GND to AGND –0.3 V to 0.3 V
PWM_X, OC_ADJ, M1, M2, M3 to AGND –0.3 V to 4.2 V
RESET_X, FAULT, OTW to AGND –0.3 V to 7 V
Maximum continuous sink current (FAULT, OTW) 9 mA
Maximum operating junction temperature range, TJ –40°C to 150°C
Storage temperature, Tstg –55°C to 150°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) These voltages represent the dc voltage + peak ac waveform measured at the terminal of the device in all conditions.

RECOMMENDED OPERATING CONDITIONS

PARAMETER DESCRIPTION MIN NOM MAX UNIT
PVDD_X Half bridge X (A, B, C, or D) DC supply voltage 0 50 52.5 V
GVDD_X Supply for logic regulators and gate-drive circuitry 11.4 12.3 13.2 V
VDD Digital regulator input 11.4 12.3 13.2 V
IO_pulse Pulsed peak current per output pin 12 A
IO Continuous current per output pin 5 A
FSw PWM switching frequency 500 kHz
Minimum output inductance under short-circuit condition and 4
LO μH
parallel mode
ROCP_CBC OC programming resistor range in cycle by cycle current limit 27 39 kΩ
modes, Resistor tolerance = 5%
ROCP_OCL OC programming resistor range in OC latching shutdown modes, 22 39 kΩ
Resistor tolerance = 5%
TA Operating ambient temperature -40 85 °C

Package Heat Dissipation Ratings

PARAMETER VALUE
RθJC, junction-to-case (heat slug) thermal resistance (all bridges
1°C/W
running)
This device is not intended to be used without a heatsink. Therefore,
RθJA, junction-to-ambient thermal resistance
RθJA is not specified. See the Thermal Information section.
Exposed heat slug area 80 mm2

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DEVICE INFORMATION

Pin Assignment
The DRV8402 is available in a thermally enhanced package:
• 36-pin PSOP3 package (DKD)
This package contains a heat slug that is located on the top side of the device for convenient thermal coupling to
the heatsink.
DKD PACKAGE
(TOP VIEW)

GVDD_B 1 36 GVDD_A
OTW 2 35 BST_A
FAULT 3 34 PVDD_A
PWM_A 4 33 OUT_A
RESET_AB 5 32 GND_A
PWM_B 6 31 GND_B
OC_ADJ 7 30 OUT_B
GND 8 29 PVDD_B
AGND 9 28 BST_B
VREG 10 27 BST_C
M3 11 26 PVDD_C
M2 12 25 OUT_C
M1 13 24 GND_C
PWM_C 14 23 GND_D
RESET_CD 15 22 OUT_D
PWM_D 16 21 PVDD_D
VDD 17 20 BST_D
GVDD_C 18 19 GVDD_D

MODE Selection Pins

MODE PINS OUTPUT
DESCRIPTION
M3 M2 M1 CONFIGURATION
0 0 0 2 FB Dual full bridge with cycle-by-cycle current limit
0 0 1 2 FB Dual full bridge with OC latching shutdown (no cycle-by-cycle current limit)
0 1 0 1 PFB Parallel full bridge with cycle-by-cycle current limit
0 1 1 1 PFB Parallel full bridge with OC latching shutdown
Half bridge with cycle-by-cycle current limit. Protection works similarly to full
bridge mode. Only difference in half bridge mode is that OUT_X is Hi-Z
1 0 0 4 HB
instead of a pulldown through internal pulldown resistor when RESET pin is
low.
1 0 1 Half bridge with OC latching shutdown. Protection works similarly to full
bridge mode. Only difference in half bridge mode is that OUT_X is Hi-Z
4 HB
instead of a pulldown through internal pulldown resistor when RESET pin is
low.
1 1 0
Reserved
1 1 1

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Pin Functions
PIN (1)
FUNCTION DESCRIPTION
NAME DKD NO.
AGND 9 P Analog ground
BST_A 35 P High side bootstrap supply (BST), external capacitor to OUT_A required
BST_B 28 P High side bootstrap supply (BST), external capacitor to OUT_B required
BST_C 27 P High side bootstrap supply (BST), external capacitor to OUT_C
required
BST_D 20 P High side bootstrap supply (BST), external capacitor to OUT_D
required
GND 8 P Ground
GND_A 32 P Power ground for half-bridge A
GND_B 31 P Power ground for half-bridge B
GND_C 24 P Power ground for half-bridge C
GND_D 23 P Power ground for half-bridge D
GVDD_A 36 P Gate-drive voltage supply requires 0.1-μF capacitor to AGND
GVDD_B 1 P Gate-drive voltage supply requires 0.1-μF capacitor to AGND
GVDD_C 18 P Gate-drive voltage supply requires 0.1-μF capacitor to AGND
GVDD_D 19 P Gate-drive voltage supply requires 0.1-μF capacitor to AGND
M1 13 I Mode selection pin
M2 12 I Mode selection pin
M3 11 I Mode selection pin
OC_ADJ 7 O Analog overcurrent programming pin requires resistor to ground
OTW 2 O Overtemperature warning signal, open-drain, active-low
OUT_A 33 O Output, half-bridge A
OUT_B 30 O Output, half-bridge B
OUT_C 25 O Output, half-bridge C
OUT_D 22 O Output, half-bridge D
PVDD_A 34 P Power supply input for half-bridge A requires close decoupling of
0.01-μF capacitor in parallel with a 1.0-μF capacitor to GND_A.
PVDD_B 29 P Power supply input for half-bridge B requires close decoupling of
0.01-μF capacitor in parallel with a 1.0-μF capacitor to GND_B.
PVDD_C 26 P Power supply input for half-bridge C requires close decoupling of
0.01-μF capacitor in parallel with a 1.0-μF capacitor to GND_C.
PVDD_D 21 P Power supply input for half-bridge D requires close decoupling of
0.01-μF capacitor in parallel with a 1.0-μF capacitor to GND_D.
PWM_A 4 I Input signal for half-bridge A
PWM_B 6 I Input signal for half-bridge B
PWM_C 14 I Input signal for half-bridge C
PWM_D 16 I Input signal for half-bridge D
RESET_AB 5 I Reset signal for half-bridge A and half-bridge B, active-low
RESET_CD 15 I Reset signal for half-bridge C and half-bridge D, active-low
FAULT 3 O Fault signal, open-drain, active-low
VDD 17 P Power supply for digital voltage regulator requires a 47-μF capacitor in
parallel with a 0.1-μF capacitor to GND for decoupling.
VREG 10 P Digital regulator supply filter pin requires 0.1-μF capacitor to AGND.

(1) I = input, O = output, P = power

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SYSTEM BLOCK DIAGRAM

4 VDD
Under-
OTW voltage 4
Protection
Internal Pullup VREG VREG
Resistors to VREG

FAULT
Power
On
M1
Reset AGND
Protection
M2 and
I/O Logic
M3 Temp.
Sense GND

RESET_AB
Overload
RESET_CD Isense OC_ADJ
Protection

GVDD_D
BST_D
PVDD_D
PWM Gate
PWM_D Ctrl. Timing OUT_D
Rcv. Drive
FB/PFB−Configuration
Pulldown Resistor

GND_D
GVDD_C
BST_C
PVDD_C
PWM Gate
PWM_C Ctrl. Timing OUT_C
Rcv. Drive
FB/PFB−Configuration
Pulldown Resistor

GND_C
GVDD_B
BST_B
PVDD_B
PWM Gate
PWM_B Ctrl. Timing OUT_B
Rcv. Drive
FB/PFB−Configuration
Pulldown Resistor

GND_B
GVDD_A
BST_A
PVDD_A
PWM Gate
PWM_A Ctrl. Timing OUT_A
Rcv. Drive
FB/PFB−Configuration
Pulldown Resistor

GND_A

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ELECTRICAL CHARACTERISTICS
Ta = 25 °C, PVDD = 50 V, GVDD = VDD = 12 V, FSw = 400 kHz, unless otherwise noted. All performance is in accordance
with recommended operating conditions unless otherwise specified.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Internal Voltage Regulator and Current Consumption
Voltage regulator, only used as a
VREG VDD = 12 V 2.95 3.3 3.65 V
reference node
IVDD VDD supply current Idle, reset mode 9 12 mA
IGVDD_X Gate supply current per half-bridge Reset mode 1.7 2 mA
IPVDD_X Half-bridge X (A, B, C, or D) idle current Reset mode 0.5 1 mA
Output Stage
MOSFET drain-to-source resistance, low TJ = 25°C, includes metallization resistance,
90 mΩ
side (LS) GVDD = 12 V
RDS(on)
MOSFET drain-to-source resistance, high TJ = 25°C, includes metallization resistance,
90 mΩ
side (HS) GVDD = 12 V
VF Diode forward voltage drop TJ = 25°C - 125°C, IO = 5 A 1 V
tR Output rise time Resistive load, IO = 5 A 9 nS
tF Output fall time Resistive load, IO = 5 A 9 nS
tPD_ON Propagation delay when FET is on Resistive load, IO = 5 A 42 nS
tPD_OFF Propagation delay when FET is off Resistive load, IO = 5 A 40 nS
tDT Dead time between HS and LS FETs Resistive load, IO = 5 A 5 nS
I/O Protection
Gate supply voltage GVDD_X
Vuvp,G 8.5 V
undervoltage protection
(1) Hysteresis for gate supply undervoltage
Vuvp,hyst 0.8 V
event
(1)
OTW Overtemperature warning 115 125 135 °C
(1) Hysteresis temperature to reset OTW
OTWhyst 25 °C
event
(1)
OTSD Overtemperature shut down 150 °C
OTE-OTWdifferential OTE-OTW overtemperature detect
(1) 25 °C
temperature difference
(1) Hysteresis temperature for FAULT to be
OTSDHYST 25 °C
released following an OTSD event.
IOC Overcurrent limit protection Resistor—programmable, nominal, ROCP = 27 kΩ 10.6 A
Time from application of short condition to Hi-Z of
IOCT Overcurrent response time 250 ns
affected FET(s)
Connected when RESET_AB or RESET_CD is
Internal pulldown resistor at the output of
RPD active to provide bootstrap capacitor charge. Not 1 kΩ
each half-bridge
used in SE mode
Static Digital Specifications
VIH High-level input voltage PWM_A, PWM_B, PWM_C, PWM_D, M1, M2, M3, 2 V
VIL Low-level input voltage RESET_AB, RESET_CD 0.8 V
llkg Input leakage current -100 100 μA
OTW / FAULT
Internal pullup resistance, OTW to
RINT_PU 20 26 35 kΩ
VREG, FAULT to VREG
Internal pullup resistor only 2.95 3.3 3.65
VOH High-level output voltage V
External pullup of 4.7 kΩ to 5 V 4.5 5
VOL Low-level output voltage IO = 4 mA 0.2 0.4 V

(1) Specified by design

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TYPICAL CHARACTERISTICS
EFFICIENCY NORMALIZED RDS(on)
vs vs
SWITCHING FREQUENCY GATE DRIVE, GVDD
100 1.10
TJ = 25°C
90
1.08

Normalized RDS(on) / (RDS(on) at 12 V)

80

70 1.06
Efficiency – %

60
1.04
50
1.02
40

30 1.00
Full Bridge
20 Load = 5 A
PVDD = 50 V 0.98
10 TC = 75°C

0 0.96
0 50 100 150 200 250 300 350 400 450 500 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12
f – Switching Frequency – kHz GVDD – Gate Drive – V
Figure 1. Figure 2.

NORMALIZED RDS(on)
vs DRAIN TO SOURCE DIODE FORWARD
JUNCTION TEMPERATURE ON CHARACTERISTICS
1.6 6
GVDD = 12 V TJ = 25°C
5
Normalized RDS(on) / (RDS(on) at 25oC)

1.4

4
1.2
I – Current – A

3
1.0
2

0.8
1

0.6 0

0.4 –1
–40 –20 0 20 40 60 80 100 120 140 0 0.2 0.4 0.6 0.8 1 1.2
o
TJ – Junction Temperature – C V – Voltage – V
Figure 3. Figure 4.

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TYPICAL CHARACTERISTICS (continued)

OUTPUT DUTY CYCLE
vs
INPUT DUTY CYCLE
100
fS = 500 kHz
90
TC = 25°C
80

Output Duty Cycle – %

70

60

50

40

30

20

10

0
0 10 20 30 40 50 60 70 80 90 100
Input Duty Cycle – %
Figure 5.

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THEORY OF OPERATION

Special attention should be paid to the power-stage

POWER SUPPLIES power supply; this includes component selection,
To help with system design, the DRV8402 needs only PCB placement, and routing. As indicated, each
a 12 V supply in addition to power-stage supply. An half-bridge has independent power-stage supply pins
internal voltage regulator provides suitable voltage (PVDD_X). For optimal electrical performance, EMI
levels for the digital and low-voltage analog circuitry. compliance, and system reliability, it is important that
Additionally, all circuitry requiring a floating voltage each PVDD_X pin is decoupled with a ceramic
supply, for example, the high-side gate drive, is capacitor placed as close as possible to each supply
accommodated by built-in bootstrap circuitry requiring pin. It is recommended to follow the PCB layout of
only a few external capacitors. the DRV8402 in EVM board.
To provide electrical characteristics, the PWM signal The 12 V supply should be from a low-noise,
path including gate drive and output stage is low-output-impedance voltage regulator. Likewise, the
designed as identical, independent half-bridges. For 50 V power-stage supply is assumed to have low
this reason, each half-bridge has separate gate drive output impedance and low noise. The power-supply
supply (GVDD_X), bootstrap pins (BST_X), and sequence is not critical as facilitated by the internal
power-stage supply pins (PVDD_X). Furthermore, an power-on-reset circuit. Moreover, the DRV8402 is
additional pin (VDD) is provided as supply for all fully protected against erroneous power-stage turn-on
common circuits. Although supplied from the same due to parasitic gate charging. Thus, voltage-supply
12-V source, it is recommended that a 1 – 10 Ω ramp rates (dv/dt) are non-critical within the specified
resistor is used to separate the GVDD_X pins from range (see the Recommended Operating Conditions
VDD on the printed-circuit board (PCB). Special section of this data sheet).
attention should be paid to placing all decoupling
capacitors as close to their associated pins as SYSTEM POWER-UP/POWER-DOWN
possible. In general, inductance between the power SEQUENCE
supply pins and decoupling capacitors must be
avoided. Powering Up
For a properly functioning bootstrap circuit, a small The DRV8402 does not require a power-up
ceramic capacitor must be connected from each sequence. The outputs of the H-bridges remain in a
bootstrap pin (BST_X) to the power-stage output pin high-impedance state until the gate-drive supply
(OUT_X). When the power-stage output is low, the voltage (GVDD_X) and VDD voltage are above the
bootstrap capacitor is charged through an internal undervoltage protection (UVP) voltage threshold (see
diode connected between the gate-drive the Electrical Characteristics section of this data
power-supply pin (GVDD_X) and the bootstrap pin. sheet). Although not specifically required, holding
When the power-stage output is high, the bootstrap RESET_AB and RESET_CD in a low state while
capacitor potential is shifted above the output powering up the device is recommended. This allows
potential and thus provides a suitable voltage supply an internal circuit to charge the external bootstrap
for the high-side gate driver. In an application with capacitors by enabling a weak pulldown of the
PWM switching frequencies in the range from 25 kHz half-bridge output (except in half-bridge modes).
to 500 kHz, the use of 47 nF ceramic capacitors, size
0603 or 0805, is recommended for the bootstrap Powering Down
supply. These 47 nF capacitors ensure sufficient
The DRV8402 does not require a power-down
energy storage, even during minimal PWM duty
sequence. The device remains fully operational as
cycles, to keep the high-side power stage FET fully
long as the gate-drive supply (GVDD_X) voltage and
turned on during the remaining part of the PWM
VDD voltage are above the UVP voltage threshold
cycle. In an application running at a switching
(see the Electrical Characteristics section of this data
frequency lower than 25 kHz, the bootstrap capacitor
sheet). Although not specifically required, it is a good
might need to be increased in value.
practice to hold RESET_AB and RESET_CD low
during power down to prevent any unknown state
during this transition.

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ERROR REPORTING Bootstrap Capacitor Under Voltage Protection

The FAULT and OTW pins are both active-low, When the device runs at a low switching frequency
open-drain outputs. Their function is for (e.g. less than 20 kHz with 47 nF bootstrap
protection-mode signaling to a PWM controller or capacitor), the bootstrap capacitor voltage might not
other system-control device. be able to maintain a proper voltage level for the
high-side gate driver. A bootstrap capacitor
Any fault resulting in device shutdown is signaled by undervoltage protection circuit (BST_UVP) will start
the FAULT pin going low. Likewise, OTW goes low under this circumstance to prevent the potential
when the device junction temperature exceeds 125°C failure of the high-side MOSFET. When the voltage
(see Table 1). on the bootstrap capacitors is less than required for
safe operation, the DRV8402 will initiate bootstrap
Table 1. capacitor recharge sequences (turn off high side FET
FAULT OTW DESCRIPTION for a short period) until the bootstrap capacitors are
0 0 Overtemperature warning and properly charged for safe operation. This function
(overtemperature shut down or overcurrent may also be activated when PWM duty cycle is too
shut down or undervoltage protection) high (e.g. higher than 99.5%). Note that bootstrap
occurred capacitor might not be able to be charged up if no
0 1 Overcurrent shut-down or undervoltage load is presented at output.
protection occurred
1 0 Overtemperature warning
Because the extra pulse width to charge bootstrap
capacitor is so short, that the output current
1 1 Device under normal operation
disruption due to the extra charge is negligible most
of the time when output inductor is present.
Note that asserting either RESET_AB or RESET_CD
low forces the FAULT signal high, independent of
Overcurrent (OC) Protection
faults being present. For proper error reporting, set
both RESET_AB and RESET_CD high during normal The device has independent, fast-reacting current
operation. detectors with programmable trip threshold (OC
threshold) on all high-side and low-side power-stage
TI recommends monitoring the OTW signal using the
FETs. There are two settings for OC protection
system microcontroller and responding to an OTW
through Mode selection pins: cycle-by-cycle (CBC)
signal by reducing the load current to prevent further
current limiting mode and OC latching (OCL) shut
heating of the device resulting in device
down mode.
overtemperature shutdown (OTSD).
In CBC current limiting mode, the detector outputs
To reduce external component count, an internal
are monitored by two protection systems. The first
pullup resistor to 3.3 V is provided on both FAULT
protection system controls the power stage in order to
and OTW outputs. Level compliance for 5-V logic can
prevent the output current from further increasing,
be obtained by adding external pull-up resistors to 5
i.e., it performs a CBC current-limiting function rather
V (see the Electrical Characteristics section of this
than prematurely shutting down the device. This
data sheet for further specifications).
feature could effectively limit the inrush current during
motor start-up or transient without damaging the
DEVICE PROTECTION SYSTEM device. During short to power and short to ground
The DRV8402 contains advanced protection circuitry condition, the current limit circuitry might not be able
carefully designed to facilitate system integration and to control the current in a proper level, a second
ease of use, as well as to safeguard the device from protection system triggers a latching shutdown,
permanent failure due to a wide range of fault resulting in the power stage being set in the
conditions such as short circuits, overcurrent, high-impedance (Hi-Z) state. Current limiting and
overtemperature, and undervoltage. The DRV8402 overcurrent protection are independent for
responds to a fault by immediately setting the power half-bridges A, B, C, and, D, respectively.
stage in a high-impedance (Hi-Z) state and asserting In OCL shut down mode, the cycle-by-cycle current
the FAULT pin low. In situations other than limit and error recovery circuitry is disabled and an
overcurrent or overtemperature, the device overcurrent condition will cause the device to
automatically recovers when the fault condition has shutdown immediately. After shutdown, RESET_AB
been removed or the gate supply voltage has and/or RESET_CD must be asserted to restore
increased. For highest possible reliability, recovering normal operation after the overcurrent condition is
from an overcurrent shut down (OCSD) or OTSD fault removed.
requires external reset of the device (see the Device
Reset section of this data sheet) no sooner than 1
second after the shutdown.

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For added flexibility, the OC threshold is Undervoltage Protection (UVP) and Power-On
programmable within a limited range using a single Reset (POR)
external resistor connected between the OC_ADJ pin The UVP and POR circuits of the DRV8402 fully
and AGND pin. See Table 2 for information on the protect the device in any power-up/down and
correlation between programming-resistor value and brownout situation. While powering up, the POR
the OC threshold. It should be noted that a properly circuit resets the overcurrent circuit and ensures that
functioning overcurrent detector assumes the all circuits are fully operational when the GVDD_X
presence of a proper inductor at the power-stage and VDD supply voltages reach 9.8 V (typical).
output (minimum 2 μH). Short-circuit protection is not Although GVDD_X and VDD are independently
provided directly at the output pins of the power monitored, a supply voltage drop below the UVP
stage, but only after the inductor. If a further smaller threshold on any VDD or GVDD_X pin results in all
inductor is preferred for any reason, using OCL mode half-bridge outputs immediately being set in the
setting is recommended. high-impedance (Hi-Z) state and FAULT being
asserted low. The device automatically resumes
Table 2. operation when all supply voltage on the bootstrap
OC-Adjust Resistor Values Max. Current Before OC Occurs capacitors have increased above the UVP threshold.
(kΩ) (A)
22 (1) 12.2 DEVICE RESET
(1)
24 11.5 Two reset pins are provided for independent control
27 10.6 of half-bridges A/B and C/D. When RESET_AB is
30 9.9 asserted low, all four power-stage FETs in
33 9.3 half-bridges A and B are forced into a
36 8.7
high-impedance (Hi-Z) state. Likewise, asserting
RESET_CD low forces all four power-stage FETs in
39 8.2 half-bridges C and D into a high-impedance state.

Overtemperature Protection In full bridge and parallel full bridge configurations, to

accommodate bootstrap charging prior to switching
The DRV8402 has a two-level temperature-protection start, asserting the reset inputs low enables weak
system that asserts an active-low warning signal pulldown of the half-bridge outputs. In half bridge
(OTW) when the device junction temperature configuration, the weak pulldowns are not enabled,
exceeds 125°C (nominal) and, if the device junction and it is, therefore, recommended to precharge
temperature exceeds 150°C (nominal), the device is bootstrap capacitor by providing a low pulse on the
put into thermal shutdown, resulting in all half-bridge PWM inputs first when reset is asserted high.
outputs being set in the high-impedance (Hi-Z) state
and FAULT being asserted low. OTSD is latched in Asserting either reset input low removes any fault
this case and RESET_AB and RESET_CD must be information to be signaled on the FAULT output, i.e.,
asserted low. FAULT is forced high.
A rising-edge transition on either reset input allows
the device to resume operation after an overcurrent
(1) Recommended to use in OCL Mode Only fault.

Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Link(s): DRV8402
 Not Recommended for New Designs
DRV8402
SLES222 – FEBRUARY 2009 www.ti.com

DIFFERENT MODE OPERATIONS

The DRV8402 supports three different mode
operations:
1. Full bridge (FB) mode
2. Parallel full bridge (PFB) mode
3. Half bridge (HB) mode
In full bridge and half bridge modes, PWM_A controls
half bridge A, PWM_B controls both half bridge B,
etc. Figure 6 shows an application example for full
bridge mode operation.
In parallel full bridge mode, PWM_A controls both
half bridge A and B, and PWM_B controls both half
bridge C and D, while PWM_C and PWM_D pins are
not used (recommended to connect to ground).
Bridges A and B are synchronized internally (even
during CBC), and so as bridges C and D. OUT_A and
OUT_B should be connected together and OUT_C Figure 6. Application Diagram Example for Full
and OUT_D should be connected together after a Bridge Mode Operation
small output inductor. Figure 7 shows an example of
parallel full bridge mode connection.
Mode pins are configured as CBC current limit
operation in Figure 6 and Figure 7.
The DRV8402 can be also used in three phase
permanent magnet synchronous motor (PMSM)
applications. Because each half bridge has
independent supply and ground pins, a shunt sensing
resistor can be inserted between PVDD to PVDD_X
or GND to GND_X. A high side shunt resistor
between PVDD and PVDD_X is recommended for
differential current sensing because a high bias
voltage on the low side sensing could affect device
operation. OCL mode is recommended for a three
phase application. Figure 8 shows a three-phase
application example.
A decoupling capacitor close to each supply pin is
recommended for each application (not shown in
diagrams). PWM_A controls OUT_A and OUT_B;
PWM_B controls OUT_C and OUT_D.

Figure 7. Application Diagram Example for

Parallel Full Bridge Mode Operation

12 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated

Product Folder Link(s): DRV8402

 Not Recommended for New Designs
DRV8402
www.ti.com SLES222 – FEBRUARY 2009

RθJA is a system thermal resistance from junction to

ambient air. As such, it is a system parameter with
the following components:
• RθJC (the thermal resistance from junction to case,
or in this example the heat slug)
• Thermal grease thermal resistance
• Heat sink thermal resistance
The thermal grease thermal resistance can be
calculated from the exposed heat slug area and the
thermal grease manufacturer's area thermal
resistance (expressed in °C-in2/W or °C-mm2/W). The
approximate exposed heat slug size is as follows:
• DRV8402, 36-pin PSOP3 …… 0.124 in2 (80 mm2)
The thermal resistance of thermal pads is considered
higher than a thin thermal grease layer. Thermal tape
has an even higher thermal resistance and should not
Figure 8. Application Diagram Example for Three be used at all. Heat sink thermal resistance is
Phase PMSM Operation predicted by the heat sink vendor, modeled using a
continuous flow dynamics (CFD) model, or measured.
Thus the system RθJA = RθJC + thermal grease
THERMAL INFORMATION resistance + heat sink resistance.
The thermally enhanced package provided with the See the TI application report, IC Package Thermal
DRV8402 is designed to interface directly to heat sink Metrics (SPRA953A), for more thermal information.
using a thermal interface compound, (e.g., Arctic
Silver, TIMTronics 413, Ceramic thermal compound,
etc.). The heat sink then absorbs heat from the ICs
and couples it to the local air.

Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Link(s): DRV8402
 PACKAGE OPTION ADDENDUM

www.ti.com 30-Sep-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DRV8402DKD LIFEBUY HSSOP DKD 36 29 RoHS & Green NIPDAU Level-4-260C-72 HR -40 to 85 DRV8402
DRV8402DKDR LIFEBUY HSSOP DKD 36 500 RoHS & Green NIPDAU Level-4-260C-72 HR -40 to 85 DRV8402

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8402DKDR HSSOP DKD 36 500 330.0 24.4 14.7 16.4 4.0 20.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV8402DKDR HSSOP DKD 36 500 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
DRV8402DKD DKD HSSOP 36 29 508 18.54 6350 8.13

Pack Materials-Page 3
 PACKAGE OUTLINE
DKD0036A SCALE 1.000
PowerPAD TM SSOP - 3.6 mm max height
PLASTIC SMALL OUTLINE

C
14.5 SEATING PLANE
TYP
13.9
A
PIN 1 ID AREA 0.1 C

34X 0.65
36
1

EXPOSED
THERMAL PAD
12.7 2X
16.0 12.6
11.05
15.8
NOTE 3

18
19
0.38
36X
0.25
0.12 C A B
(2.95)

5.9
5.8
11.1
B
10.9
NOTE 4
(0.15)
EXPOSED THERMAL PAD

3.6
3.1

(0.28) TYP
SEE DETAIL A
0.35
GAGE PLANE

1.1 0.3
0 -8 0.8 0.1

DETAIL A
TYPICAL

4222166/B 06/2017
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. The exposed thermal pad is designed to be attached to an external heatsink.

www.ti.com
 EXAMPLE BOARD LAYOUT
DKD0036A PowerPAD TM SSOP - 3.6 mm max height
PLASTIC SMALL OUTLINE

36X (2) SEE DETAILS

SYMM
1
36

36X (0.45)

34X (0.65)

SYMM

(R0.05) TYP

18 19

(13.2)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:6X

SOLDER MASK METAL UNDER

SOLDER MASK METAL
OPENING SOLDER MASK
OPENING

EXPOSED
METAL EXPOSED
0.05 MAX 0.05 MIN METAL
AROUND AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE
4222166/B 06/2017
NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
DKD0036A PowerPAD TM SSOP - 3.6 mm max height
PLASTIC SMALL OUTLINE

36X (2)
SYMM
1
36

36X (0.45)

34X (0.65)
SYMM

(R0.05) TYP

18 19

(13.2)

SOLDER PASTE EXAMPLE

BASED ON 0.125 MM THICK STENCIL
SCALE:6X

4222166/B 06/2017
NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
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