Features

• Low-voltage and Standard-voltage Operation

– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 2.5 (VCC = 2.5V to 5.5V)
– 1.8 (VCC = 1.8V to 3.6V)
• Internally Organized 16,384 x 8 and 32,768 x 8
• 2-wire Serial Interface
• Schmitt Trigger, Filtered Inputs for Noise Suppression
• Bidirectional Data Transfer Protocol
• 1 MHz (5V), 400 kHz (2.7V, 2.5V) and 100 kHz (1.8V) Compatibility
• Write Protect Pin for Hardware and Software Data Protection
• 64-byte Page Write Mode (Partial Page Writes Allowed) 2-wire Serial
• Self-timed Write Cycle (5 ms Typical)
• High Reliability EEPROMs
– Endurance: 100,000 Write Cycles
– Data Retention: 40 Years 128K (16,384 x 8)
– ESD Protection: >4000V
• Automotive Grade and Extended Temperature Devices Available
• 8-pin JEDEC PDIP, 8-pin JEDEC and EIAJ SOIC, 14-pin TSSOP, 8-pin Leadless Array,
256K (32,768 x 8)
and 8-ball dBGATM Packages

Description AT24C128
The AT24C128/256 provides 131,072/262,144 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 16,384/32,768 words of 8 AT24C256
bits each. The device’s cascadable feature allows up to 4 devices to share a common
2-wire bus. The device is optimized for use in many industrial and commercial applica-
tions where low power and low voltage operation are essential. The devices are
available in space-saving 8-pin JEDEC PDIP, 8-pin EIAJ, 8-pin JEDEC SOIC, 14-pin
TSSOP, 8-pin LAP, and 8-ball dBGA packages. In addition, the entire family is avail-
able in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to
3.6V) versions.

Pin Configurations 8-pin PDIP 8-pin SOIC

Pin Name Function A0 1 8 VCC A0 1 8 VCC

A1 2 7 WP A1 2 7 WP
A0 - A1 Address Inputs NC 3 6 SCL NC 3 6 SCL
GND 4 5 SDA GND 4 5 SDA
SDA Serial Data
SCL Serial Clock Input
WP Write Protect 8-pin Leadless Array 8-ball dBGA
NC No Connect VCC 8 1 A0
VCC 8 1 A0
WP 7 2 A1
WP 7 2 A1
SCL 6 3 NC
SCL 6 3 NC
SDA 5 4 GND
SDA 5 4 GND

Bottom View Bottom View

14-pin TSSOP

A0 1 14 VCC
A1 2 13 WP
NC 3 12 NC
NC 4 11 NC
NC 5 10 NC
NC 6 9 SCL
GND 7 8 SDA Rev. 0670E–07/01

1
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
Storage Temperature ..................................... -65°C to +150°C age to the device. This is a stress rating only and
functional operation of the device at these or any
Voltage on Any Pin other conditions beyond those indicated in the
with Respect to Ground .....................................-1.0V to +7.0V operational sections of this specification is not
implied. Exposure to absolute maximum rating
Maximum Operating Voltage .......................................... 6.25V conditions for extended periods may affect device
reliability.
DC Output Current........................................................ 5.0 mA

Block Diagram

2 AT24C128/256
0670E–07/01
 AT24C128/256

Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-
drain driven and may be wire-ORed with any number of other open-drain or open collector
devices.
DEVICE/PAGE ADDRESSES (A1, A0): The A1 and A0 pins are device address inputs that
are hardwired or left not connected for hardware compatibility with AT24C32/64. When the
pins are hardwired, as many as four 128K/256K devices may be addressed on a single bus
system (device addressing is discussed in detail under the Device Addressing section). When
the pins are not hardwired, the default A1 and A0 are zero.
WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write oper-
ations. When WP is tied high to VCC, all write operations to the memory are inhibited. If left
unconnected, WP is internally pulled down to GND. Switching WP to VCC prior to a write oper-
ation creates a software write protect function.

Memory AT24C128/256, 128K/256K SERIAL EEPROM: The 128K/256K is internally organized as

Organization 256/512 pages of 64-bytes each. Random word addressing requires a 14/15-bit data word
address.

3
0670E–07/01
Pin Capacitance(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V.
Symbol Test Condition Max Units Conditions
CI/O Input/Output Capacitance (SDA) 8 pF VI/O = 0V
CIN Input Capacitance (A0, A1, SCL) 6 pF VIN = 0V

Note: 1. This parameter is characterized and is not 100% tested.

DC Characteristics(1)
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V, TAC = 0°C to +70°C,
VCC = +1.8V to +5.5V (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Units
VCC1 Supply Voltage 1.8 3.6 V
VCC2 Supply Voltage 2.5 5.5 V
VCC3 Supply Voltage 4.5 5.5 V
ICC1 Supply Current VCC = 5.0V READ at 400 kHz 1.0 2.0 mA
ICC2 Supply Current VCC = 5.0V WRITE at 400 kHz 2.0 3.0 mA

Standby Current VCC = 1.8V 0.2 µA

ISB1 VIN = VCC or VSS
(1.8V option) VCC = 3.6V 2.0

Standby Current VCC = 2.5V 0.5 µA

ISB2 VIN = VCC or VSS
(2.5V option) VCC = 5.5V 6.0
Standby Current
ISB3 VCC = 4.5 - 5.5V VIN = VCC or VSS 6.0 µA
(5.0V option)
ILI Input Leakage Current VIN = VCC or VSS 0.10 3.0 µA
Output Leakage
ILO VOUT = VCC or VSS 0.05 3.0 µA
Current
VIL Input Low Level(1) -0.6 VCC x 0.3 V
VIH Input High Level(1) VCC x 0.7 VCC + 0.5 V
VOL2 Output Low Level VCC = 3.0V IOL = 2.1 mA 0.4 V
VOL1 Output Low Level VCC = 1.8V IOL = 0.15 mA 0.2 V

Note: 1. VIL min and VIH max are reference only and are not tested

4 AT24C128/256
0670E–07/01
 AT24C128/256

AC Characteristics
Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +1.8V to +5.5V, CL = 100 pF (unless oth-
erwise noted). Test conditions are listed in Note 2.
1.8-volt 2.5-volt 5.0-volt
Symbol Parameter Min Max Min Max Min Max Units
fSCL Clock Frequency, SCL 100 400 1000 kHz
tLOW Clock Pulse Width Low 4.7 1.3 0.6 µs
tHIGH Clock Pulse Width High 4.0 1.0 0.4 µs
tAA Clock Low to Data Out Valid 0.1 4.5 0.05 0.9 0.05 0.55 µs
Time the bus must be free before a new
tBUF 4.7 1.3 0.5 µs
transmission can start(1)
tHD.STA Start Hold Time 4.0 0.6 0.25 µs
tSU.STA Start Set-up Time 4.7 0.6 0.25 µs
tHD.DAT Data In Hold Time 0 0 0 µs
tSU.DAT Data In Set-up Time 200 100 100 ns
tR Inputs Rise Time (1)
1.0 0.3 0.3 µs
(1)
tF Inputs Fall Time 300 300 100 ns
tSU.STO Stop Set-up Time 4.7 0.6 0.25 µs
tDH Data Out Hold Time 100 50 50 ns
tWR Write Cycle Time 20 10 10 ms
Write
Endurance(1) 5.0V, 25°C, Page Mode 100K 100K 100K
Cycles

Notes: 1. This parameter is characterized and is not 100% tested.

2. AC measurement conditions:
RL (connects to VCC): 1.3KΩ (2.5V, 5V), 10KΩ (1.8V)
Input pulse voltages: 0.3VCC to 0.7VCC
Input rise and fall times: ≤50ns
Input and output timing reference voltages: 0.5VCC

5
0670E–07/01
Device CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
Operation device. Data on the SDA pin may change only during SCL low time periods (refer to Data
Validity timing diagram). Data changes during SCL high periods will indicate a start or stop
condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (refer to Start and Stop Definition timing diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (refer to
Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-
edge that it has received each word.
STANDBY MODE: The AT24C128/256 features a low power standby mode which is enabled:
a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal
operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire
part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in
each cycle while SCL is high and then (c) create a start condition as SDA is high.

6 AT24C128/256
0670E–07/01
 AT24C128/256

Bus Timing (SCL: Serial Clock, SDA: Serial Data I/O)

Write Cycle Timing (SCL: Serial Clock, SDA: Serial Data I/O)

SCL

SDA 8th BIT ACK

WORD n (1)
tWR
STOP START
CONDITION CONDITION
Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.

7
0670E–07/01
Data Validity

Start and Stop Definition

Output Acknowledge

8 AT24C128/256
0670E–07/01
 AT24C128/256

Device The 128K/256K EEPROM requires an 8-bit device address word following a start condition to
Addressing enable the chip for a read or write operation (refer to Figure 1). The device address word con-
sists of a mandatory one, zero sequence for the first five most significant bits as shown. This is
common to all 2-wire EEPROM devices.
The 128K/256K uses the two device address bits A1, A0 to allow as many as four devices on
the same bus. These bits must compare to their corresponding hardwired input pins. The A1
and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the
pins are allowed to float.
The eighth bit of the device address is the read/write operation select bit. A read operation is
initiated if this bit is high and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will output a zero. If a compare is not
made, the device will return to a standby state.
DATA SECURITY: The AT24C128/256 has a hardware data protection scheme that allows the
user to write protect the whole memory when the WP pin is at VCC.

Write BYTE WRITE: A write operation requires two 8-bit data word addresses following the device
Operations address word and acknowledgment. Upon receipt of this address, the EEPROM will again
respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit
data word, the EEPROM will output a zero. The addressing device, such as a microcontroller,
then must terminate the write sequence with a stop condition. At this time the EEPROM
enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled
during this write cycle and the EEPROM will not respond until the write is complete (refer to
Figure 2).
PAGE WRITE: The 128K/256K EEPROM is capable of 64-byte page writes.
A page write is initiated the same way as a byte write, but the microcontroller does not send a
stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges
receipt of the first data word, the microcontroller can transmit up to 63 more data words. The
EEPROM will respond with a zero after each data word received. The microcontroller must
terminate the page write sequence with a stop condition (refer to Figure 3).
The data word address lower 6 bits are internally incremented following the receipt of each
data word. The higher data word address bits are not incremented, retaining the memory page
row location. When the word address, internally generated, reaches the page boundary, the
following byte is placed at the beginning of the same page. If more than 64 data words are
transmitted to the EEPROM, the data word address will “roll over” and previous data will be
overwritten. The address “roll over” during write is from the last byte of the current page to the
first byte of the same page.
ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the
EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a
start condition followed by the device address word. The read/write bit is representative of the
operation desired. Only if the internal write cycle has completed will the EEPROM respond
with a zero, allowing the read or write sequence to continue.

9
0670E–07/01
Read Read operations are initiated the same way as write operations with the exception that the
Operations read/write select bit in the device address word is set to one. There are three read operations:
current address read, random address read and sequential read.
CURRENT ADDRESS READ: The internal data word address counter maintains the last
address accessed during the last read or write operation, incremented by one. This address
stays valid between operations as long as the chip power is maintained. The address “roll
over” during read is from the last byte of the last memory page, to the first byte of the first
page.
Once the device address with the read/write select bit set to one is clocked in and acknowl-
edged by the EEPROM, the current address data word is serially clocked out. The
microcontroller does not respond with an input zero but does generate a following stop condi-
tion (refer to Figure 4).
RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data
word address. Once the device address word and data word address are clocked in and
acknowledged by the EEPROM, the microcontroller must generate another start condition.
The microcontroller now initiates a current address read by sending a device address with the
read/write select bit high. The EEPROM acknowledges the device address and serially clocks
out the data word. The microcontroller does not respond with a zero but does generate a fol-
lowing stop condition (refer to Figure 5).
SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a ran-
dom address read. After the microcontroller receives a data word, it responds with an
acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment
the data word address and serially clock out sequential data words. When the memory
address limit is reached, the data word address will “roll over” and the sequential read will con-
tinue. The sequential read operation is terminated when the microcontroller does not respond
with a zero but does generate a following stop condition (refer to Figure 6).

Figure 1. Device Address

Figure 2. Byte Write

10 AT24C128/256
0670E–07/01
 AT24C128/256

Figure 3. Page Write

Notes: (* = DON’T CARE bit)

(† = DON’T CARE bit for the 128K)

Figure 4. Current Address Read

Figure 5. Random Read

Notes: (* = DON’T CARE bit)

(† = DON’T CARE bit for the 128K)

Figure 6. Sequential Read

11
0670E–07/01
AT24C128 Ordering Information
tWR (max) ICC (max) ISB (max) fMAX
(ms) (µA) (µA) (kHz) Ordering Code Package Operation Range
10 3000 6.0 1000 AT24C128-10CC 8C Commercial
AT24C128C1-10CC 8C1 (0°C to 70°C)
AT24C128-10PC 8P3
AT24C128N-10SC 8S1
AT24C128W-10SC 8S2
AT24C128-10UC 8U1
AT24C128T1-10TC 14T
3000 6.0 1000 AT24C128-10CI 8C Industrial
AT24C128C1-10CI 8C1 (-40°C to 85°C)
AT24C128-10PI 8P3
AT24C128N-10SI 8S1
AT24C128W-10SI 8S2
AT24C128-10UI 8U1
AT24C128T1-10TI 14T
10 1500 0.5 400 AT24C128-10CC-2.7 8C Commercial
AT24C128C1-10CC-2.7 8C1 (0°C to 70°C)
AT24C128-10PC-2.7 8P3
AT24C128N-10SC-2.7 8S1
AT24C128W-10SC-2.7 8S2
AT24C128-10UC-2.7 8U1
AT24C128T1-10TC-2.7 14T
1500 0.5 400 AT24C128-10CI-2.7 8C Industrial
AT24C128C1-10CI-2.7 8C1 (-40°C to 85°C)
AT24C128-10PI-2.7 8P3
AT24C128N-10SI-2.7 8S1
AT24C128W-10SI-2.7 8S2
AT24C128-10UI-2.7 8U1
AT24C128T1-10TI-2.7 14T

Package Type
8C 8-lead, 0.230" Wide, Leadless Array Package (LAP)
8C1 8-lead, 0.300" Wide, Leadless Array Package (LAP)
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8U1 8-ball, die Ball Grid Array Package (dBGA)
14T 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
Blank Standard Operation (4.5V to 5.5V)
-2.7 Low-voltage (2.7V to 5.5V)
-1.8 Low-voltage (1.8V to 3.6V)

12 AT24C128/256
0670E–07/01
 AT24C128/256

AT24C128 Ordering Information (Continued)

tWR (max) ICC (max) ISB (max) fMAX
(ms) (µA) (µA) (kHz) Ordering Code Package Operation Range
10 1500 0.5 400 AT24C128-10PI-2.5 8P3 Industrial
AT24C128N-10SI-2.5 8S1 (-40°C to 85°C)
AT24C128W-10SI-2.5 8S2
20 800 0.2 100 AT24C128-10CC-1.8 8C Commercial
AT24C128C1-10CC-1.8 8C1 (0°C to 70°C)
AT24C128-10PC-1.8 8P3
AT24C128N-10SC-1.8 8S1
AT24C128W-10SC-1.8 8S2
AT24C128-10UC-1.8 8U1
AT24C128T1-10TC-1.8 14T
800 0.2 100 AT24C128-10CI-1.8 8C Industrial
AT24C128C1-10CI-1.8 8C1 (-40°C to 85°C)
AT24C128-10PI-1.8 8P3
AT24C128N-10SI-1.8 8S1
AT24C128W-10SI-1.8 8S2
AT24C128-10UI-1.8 8U1
AT24C128T1-10TI-1.8 14T

Package Type
8C 8-lead, 0.230" Wide, Leadless Array Package (LAP)
8C1 8-lead, 0.300" Wide, Leadless Array Package (LAP)
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8U1 8-ball, die Ball Grid Array Package (dBGA)
14T 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
Blank Standard Operation (4.5V to 5.5V)
-2.7 Low-voltage (2.7V to 5.5V)
-2.5 Low-voltage (2.5V to 5.5V)
-1.8 Low-voltage (1.8V to 3.6V)

13
0670E–07/01
AT24C256 Ordering Information
tWR (max) ICC (max) ISB (max) fMAX
(ms) (µA) (µA) (kHz) Ordering Code Package Operation Range
10 3000 6.0 1000 AT24C256-10CC 8C Commercial
AT24C256C1-10CC 8C1 (0°C to 70°C)
AT24C256-10PC 8P3
AT24C256N-10SC 8S1
AT24C256W-10SC 8S2
AT24C256-10UC 8U2
AT24C256T1-10TC 14T
3000 6.0 1000 AT24C256-10CI 8C Industrial
AT24C256C1-10CI 8C1 (-40°C to 85°C)
AT24C256-10PI 8P3
AT24C256N-10SI 8S1
AT24C256W-10SI 8S2
AT24C256-10UI 8U2
AT24C256T1-10TI 14T
10 1500 0.5 400 AT24C256-10CC-2.7 8C Commercial
AT24C256C1-10CC-2.7 8C1 (0°C to 70°C)
AT24C256-10PC-2.7 8P3
AT24C256N-10SC-2.7 8S1
AT24C256W-10SC-2.7 8S2
AT24C256-10UC-2.7 8U2
AT24C256T1-10TC-2.7 14T
1500 0.5 400 AT24C256-10CI-2.7 8C Industrial
AT24C256C1-10CI-2.7 8C1 (-40°C to 85°C)
AT24C256-10PI-2.7 8P3
AT24C256N-10SI-2.7 8S1
AT24C256W-10SI-2.7 8S2
AT24C256-10UI-2.7 8U2
AT24C256T1-10TI-2.7 14T

Package Type
8C 8-lead, 0.230" Wide, Leadless Array Package (LAP)
8C1 8-lead, 0.300" Wide, Leadless Array Package (LAP)
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8U2 8-ball, die Ball Grid Array Package (dBGA)
14T 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
Blank Standard Operation (4.5V to 5.5V)
-2.7 Low-voltage (2.7V to 5.5V)
-1.8 Low-voltage (1.8V to 3.6V)

14 AT24C128/256
0670E–07/01
 AT24C128/256

AT24C256 Ordering Information (Continued)

tWR (max) ICC (max) ISB (max) fMAX
(ms) (µA) (µA) (kHz) Ordering Code Package Operation Range
20 800 0.2 100 AT24C256-10CC-1.8 8C Commercial
AT24C256C1-10CC-1.8 8C1 (0°C to 70°C)
AT24C256-10PC-1.8 8P3
AT24C256N-10SC-1.8 8S1
AT24C256W-10SC-1.8 8S2
AT24C256-10UC-1.8 8U2
AT24C256T1-10TC-1.8 14T
800 0.2 100 AT24C256-10CI-1.8 8C Industrial
AT24C256C1-10CI-1.8 8C1 (-40°C to 85°C)
AT24C256-10PI-1.8 8P3
AT24C256N-10SI-1.8 8S1
AT24C256W-10SI-1.8 8S2
AT24C256-10UI-1.8 8U2
AT24C256T1-10TI-1.8 14T

Package Type
8C 8-lead, 0.230" Wide, Leadless Array Package (LAP)
8C1 8-lead, 0.300" Wide, Leadless Array Package (LAP)
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8U2 8-ball, die Ball Grid Array Package (dBGA)
14T 14-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
Options
Blank Standard Operation (4.5V to 5.5V)
-2.7 Low-voltage (2.7V to 5.5V)
-1.8 Low-voltage (1.8V to 3.6V)

15
0670E–07/01
Packaging Information
8C, 8-lead, 0.230" Wide, Leadless Array Package 8C1, 8-lead, 0.300" Wide, Leadless Array Package
(LAP) (LAP)
Dimensions in Millimeters and (Inches)* Dimensions in Millimeters and (Inches)*

SIDE
SIDE TOP VIEW VIEW
TOP VIEW VIEW

5.10 (0.201)
5.03 (0.198) 4.90 (0.193)
4.83 (0.190)

8.10 (0.319) 1.14 (0.045)

1.14 (0.045) 7.90 (0.311) 0.94 (0.037)
6.09 (0.240)
5.89 (0.232) 0.94 (0.037) 0.38 (0.015)
0.38 (0.015) BOTTOM VIEW 0.30 (0.012)
0.30 (0.012) 1.32 (0.052) 1.22 (0.048)
BOTTOM VIEW
1.32 (0.052) 1.19 (0.047) 1.22 (0.048) 1.12 (0.044)
1.22 (0.048) 1.09 (0.043) 8 1
8 1 0.95 (0.037)
7 2 0.85 (0.033)
0.61 (0.024)
7 2 4.76 (0.187)
0.51 (0.020) 6 3
4.66 (0.183)
6 3
5 4
5 4 0.92 (0.036)
0.34 (0.013)
0.89 (0.035) 0.82 (0.032)
0.61 (0.024) 0.24 (0.009)
0.79 (0.031)
0.51 (0.020)

*Controlling dimensions: millimeters *Controlling dimensions: millimeters

8P3, 8-lead, 0.300" Wide, 8S1, 8-lead, 0.150" Wide,

Plastic Dual Inline Package (PDIP) Plastic Gull Wing Small Outline (JEDEC SOIC)
Dimensions in Inches and (Millimeters) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 BA

.020 (.508)
.400 (10.16)
.355 (9.02) .013 (.330)

PIN
1
.157 (3.99) .244 (6.20)
.280 (7.11) .228 (5.79)
.150 (3.81)
.240 (6.10) PIN 1

.037 (.940)
.300 (7.62) REF .027 (.690)
.050 (1.27) BSC

.210 (5.33) MAX .100 (2.54) BSC

SEATING .196 (4.98)
PLANE .189 (4.80)
.068 (1.73)
.015 (.380) MIN .053 (1.35)
.150 (3.81)
.115 (2.92) .022 (.559)
.070 (1.78) .014 (.356)
.045 (1.14)
.010 (.254)
.325 (8.26)
.004 (.102)
.300 (7.62)
0 0
REF REF .010 (.254)
.012 (.305) 15 8
.007 (.203)
.008 (.203)
.430 (10.9) MAX .050 (1.27)
.016 (.406)

16 AT24C128/256
0670E–07/01
 AT24C128/256

Packaging Information
8S2, 8-lead, 0.200" Wide, 8U1, 8-ball, die Ball Grid Array Package (dBGA)
Plastic Gull Wing Small Outline (EIAJ SOIC) Dimensions in Millimeters and (Inches)*
Dimensions in Inches and (Millimeters)

.020 (.508) TOP VIEW

.012 (.305) 2.21 (0.087)

.213 (5.41) .330 (8.38)

.205 (5.21) .300 (7.62)
PIN 1
3.73 (0.147)

.050 (1.27) BSC

.212 (5.38) SIDE VIEW

.203 (5.16) BOTTOM VIEW 0.90 (0.035)
.080 (2.03)
.070 (1.78)
8 1

.013 (.330) 7 2

.004 (.102)
6 3

0 0.75 (0.029)
REF .010 (.254)
8 5 4
.007 (.178)
0.74 (0.029)

.035 (.889)
0.75 (0.029) 0.73 (0.028) 0.38 (0.015)
.020 (.508)
*Controlling dimensions: millimeters

8U2, 8-ball, die Ball Grid Array Package (dBGA) 14T, 14-lead, 0.170" Wide, Thin Shrink Small Outline
Dimensions in Millimeters and (Inches)* Package (TSSOP)
Dimensions in Millimeters and (Inches)*

TOP VIEW INDEX MARK

PIN
2.34 (0.092) 1

4.50 (.177) 6.50 (.256)

4.30 (.169) 6.25 (.246)
3.81 (0.15)

SIDE VIEW
5.10 (.201)
BOTTOM VIEW 0.90 (0.035) 1.20 (.047) MAX
4.90 (.193)

8 1
.650 (.026) BSC
0.15 (.006) SEATING
7 2 0.30 (.012) 0.05 (.002) PLANE
0.19 (.007)

6 3
0 0.20 (.008)
0.75 (0.029) REF 0.09 (.004)
8
5 4
0.78 (0.031) 0.75 (.030)
0.45 (.018)
0.75 (0.029) 0.79 (0.031) 0.38 (0.015)

*Controlling dimensions: millimeters *Controlling dimension: millimeters

17
0670E–07/01
 Atmel Headquarters Atmel Product Operations
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© Atmel Corporation 2001.

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.

ATMEL ® is the registered trademarks of Atmel; dBGA ™ is the trademark of Atmel.

Other terms and product names may be the trademarks of others.

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0670E–07/01/xM