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2019-20 Supple Coa

This document is a question paper for a Computer Organization and Architecture exam that will take place on 20-Oct-2020 from 2:00 PM to 5:30 PM. It contains 7 questions with internal choices. Students are required to answer 5 full questions. The questions cover topics like addressing modes, functional units of a computer system, addition/subtraction operations, parameter passing in functions, stack usage in subroutines, DRAM implementation, virtual address translation, cache organization, carry lookahead adders, multiplication algorithms like Booth's multiplication, division algorithms like restoring and non-restoring division, IEEE number representations, sequential binary circuit multipliers, Flynn's taxonomy of parallel architectures, differences between hardwired and microprogrammed

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26 views2 pages

2019-20 Supple Coa

This document is a question paper for a Computer Organization and Architecture exam that will take place on 20-Oct-2020 from 2:00 PM to 5:30 PM. It contains 7 questions with internal choices. Students are required to answer 5 full questions. The questions cover topics like addressing modes, functional units of a computer system, addition/subtraction operations, parameter passing in functions, stack usage in subroutines, DRAM implementation, virtual address translation, cache organization, carry lookahead adders, multiplication algorithms like Booth's multiplication, division algorithms like restoring and non-restoring division, IEEE number representations, sequential binary circuit multipliers, Flynn's taxonomy of parallel architectures, differences between hardwired and microprogrammed

Uploaded by

naveenk1999nk99
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Question Paper

Exam Date & Time: 20-Oct-2020 (02:00 PM - 05:30 PM)

BMS COLLEGE OF ENGINEERING

Autonomous Institute Affiliated to VTU, Supplementary Semester End Examinations October 2020
Comp. Organisation and Architecture [19CS3PCCOA]
Marks: 100 Duration: 210 mins.

Computer Science And Engineering-III Sem


Answer all the questions.
Instructions: 1. Answer five full questions using the given internal choice

2. Missing data, if any, may be suitably assumed.

1) Define addressing modes. Explain any five addressing modes with an example. (6)

a)
b) Explain the various functional units of digital computer system with a neat diagram. (8)
c) Perform addition and subtraction operation for the following. Also state the over flow condition. (6)
(i) -3 and - 7
(ii) +6 and +8
2) Explain the concept of parameter passing by value and reference with a program of adding two (8)
numbers.
a)
b) Explain the stack workspace created during the execution of subroutine with an example. (6)
c) Device a mechanism to handle interrupts which allows the interrupt to the processor when another (6)
interrupt is currently being served.
3) Device the implementation details in designing 16 M DRAM configured using 2 M X 8 Chip. (8)

a)
b) Demonstrate the translation of Virtual address to physical address with neat diagram. (6)
c) List and explain different types of Read Only Memories (ROM). (6)
[OR] Describe set associative memory mapping technique with a neat diagram. (6)
4)
a)
b) A cache is organized in the Direct mapped manner with the following parameter (8)
Main memory size 64 K.
Cache Size 1K
Block size 128 words
(i) How many bits are there in main memory address?
(ii) How many bits are there in each TAG,BLOCK and WORD fields
c) Describe the read and write operations that are carried out in S-RAM. (6)
5) Design 16-Bit Carry Look Ahead Adder (CLA)by cascading 4 - Bit CLA and compute the Gate delay (8)
to produce S15 and C16. Compare the Gate delay needed when 16-Bit CLA is designed using high
a) level Generate and Propagate function of 4 - Bit CLA.

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b) Multiply 2-Signed numbers using bit Pair recoding. Assume A is Multiplicand and B is a Multiplier (6)
A = 110011 and B = 101100
c) Perform Signed multiplication of numbers -12 and -10 using Booth's Multiplication Algorithm. (6)
[OR] Perform division of two numbers A = 10101 and B = 00100 using Restoring and Non-restoring (10)
6) division Algorithms and compare both the methods.
a)
b) Represent (1259.125)10 using IEEE single and double precision notation . (4)
c) Apply sequential binary circuit multiplier to multiply numbers A=15 and B=6. Show the steps of add (6)
and shift method.
7) Describe the taxonomy of Flynn's in Parallel architecture. (5)

a)
b) Illustrate the difference between hardwired and Microprogrammed Control Unit. (5)
c) With a neat diagram explain multiple bus organization of a processor and write the control (10)
sequence for Add (R4), R5.

-----End-----

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