LMH32401

SBOS965D – OCTOBER 2019 – REVISED JANUARY 2023

LMH32401 450-MHz, Programmable Gain, Differential Output Transimpedance

Amplifier

1 Features 3 Description
• Integrated programmable gain: 2 kΩ or 20 kΩ The LMH32401 device is a programmable-
• Performance, gain = 2 kΩ, CPD = 1 pF: gain, single-ended, input-to-differential output
– Bandwidth: 450 MHz transimpedance amplifier for light detection and
– Input-referred noise: 250 nARMS ranging (LIDAR) applications and laser distance
– Rise, fall time: 0.8 ns measurement systems. The LMH32401 device can be
• Performance, gain = 20 kΩ, CPD = 1 pF: configured in a gain of 2 kΩ or 20 kΩ. The LMH32401
– Bandwidth: 275 MHz device has 1.5 VPP of output swing and is designed to
– Input-referred noise: 49 nARMS drive a 100-Ω load.
– Rise, fall time: 1.3 ns The LMH32401 device has an integrated 100-mA
• Integrated ambient light cancellation clamp that protects the amplifier and allows the device
• Integrated 100-mA protection clamp to recover rapidly from an overloaded input condition.
• Integrated output multiplexer The LMH32401 device also features an integrated
• Wide output swing: 1.5 VPP ambient light cancellation circuit that can be used
• Quiescent current: 30 mA instead of AC coupling between the photodiode and
• Packages: 16-pin VQFN and bare die the amplifier to save board space in addition to
• Temperature range: –40 to +125°C reducing system cost. The ambient light cancellation
2 Applications circuit can be disabled in cases where DC coupling is
required.
• Mechanically scanning LIDAR
• Solid-state scanning LIDAR The LMH32401 device can be placed in low-power
• Laser distance meter mode using the EN pin to conserve power when
• Optical ToF position sensor the amplifier is not being used. Putting the amplifier
• Drone vision in low-power mode places its output pins in a
• Industrial robot LIDAR high-impedance state. This feature allows several
• Mobile robot LIDAR LMH32401 amplifiers to be multiplexed to a single
• Vacuum robot LIDAR ADC with the EN control pin serving as the multiplexer
select function.
Package Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LMH32401 VQFN (16) 3.00 mm × 3.00 mm

Device Information(1)
PART NUMBER PACKAGE DIE SIZE (NOM)
LMH32401 Bare die 1.025 mm × 1.060 mm

(1) For all available packagese, see the package option

addendum at the end of the data sheet.
GAIN VDD1 VDD2 EN 3
Normalized Transimpedance Gain (dB:)

1 NŸ 0
100-mA
Clamp
10 NŸ
IN Differential Output ADC -3
Driver

TIA 10 Ÿ -6
OUTí

í VBIAS Ambient Light + -9

Cancellation 2x VOCM
±
IDC EN
-12
OUT+ Gain = 2 k:
VOD Output Offset 10 Ÿ Gain = 20 k:
-15
10M 100M 1G
GND Frequency [Hz]

Simplified Block Diagram Closed-Loop Transimpedance Bandwidth

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.3 Feature Description...................................................21
2 Applications..................................................................... 1 7.4 Device Functional Modes..........................................23
3 Description.......................................................................1 8 Application and Implementation.................................. 24
4 Revision History.............................................................. 2 8.1 Application Information............................................. 24
5 Pin Configuration and Functions...................................3 8.2 Typical Application ................................................... 25
6 Specifications.................................................................. 5 9 Power Supply Recommendations................................28
6.1 Absolute Maximum Ratings........................................ 5 10 Layout...........................................................................28
6.2 ESD Ratings............................................................... 5 10.1 Layout Guidelines................................................... 28
6.3 Recommended Operating Conditions.........................5 10.2 Layout Example...................................................... 29
6.4 Thermal Information....................................................5 11 Device and Documentation Support..........................30
6.5 Electrical Characteristics: Gain = 2 kΩ....................... 6 11.1 Device Support........................................................30
6.6 Electrical Characteristics: Gain = 20 kΩ..................... 7 11.2 Documentation Support.......................................... 30
6.7 Electrical Characteristics: Both Gains.........................8 11.3 Receiving Notification of Documentation Updates.. 30
6.8 Electrical Characteristics: Logic Threshold and 11.4 Support Resources................................................. 30
Switching Characteristics............................................ 10 11.5 Trademarks............................................................. 30
6.9 Typical Characteristics.............................................. 11 11.6 Electrostatic Discharge Caution.............................. 30
7 Detailed Description......................................................20 11.7 Glossary.................................................................. 30
7.1 Overview................................................................... 20 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram......................................... 20 Information.................................................................... 31

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (August 2022) to Revision D (January 2023) Page
• Updated the backside potential information for bare die package information in the Pin Configuration and
Functions section ...............................................................................................................................................3

Changes from Revision B (February 2022) to Revision C (August 2022) Page

• Changed the status of the Bare die from: Preview to: Active ............................................................................ 1
• Updated the bare die package information in the Pin Configuration and Functions section.............................. 3

Changes from Revision A (September 2020) to Revision B (February 2022) Page

• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added bare die preview package to the Features section and Device Information table................................... 1
• Added the bare die preview package to the Pin Configuration and Functions section.......................................3

Changes from Revision * (October 2019) to Revision A (June 2020) Page

• Changed status From: Advanced Information To: Production Data ...................................................................1

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5 Pin Configuration and Functions

GAIN NC VDD2 NC

16 15 14 13

GND 1 12 VOCM

VDD1 2 11 OUTí

Thermal Pad

IN 3 10 OUT+

NC 4 9 VOD

5 6 7 8

IDC_EN EN GND NC

Not to scale

Figure 5-1. RGT Package, 16-Pin VQFN with Exposed Thermal Pad (Top View)

Table 5-1. Pin Functions

PIN
TYPE(2) DESCRIPTION
NAME NO.
EN 6 I Device enable pin. EN = logic low = normal operation (default)(1); EN = logic high = power off mode.
GAIN 16 I Gain setting. GAIN = low = 2 kΩ (default)(1); GAIN = high = 20 kΩ.
GND 1, 7 I Amplifier ground.
Ambient light cancellation (ALC) loop enable. IDC_EN = logic low = enable DC current cancellation
IDC_EN 5 I
(default)(1); IDC_EN = logc high = disable DC current cancellation.
IN 3 I Transimpedance amplifier input.
NC 4, 8, 13, 15 — No connection.
Inverting amplifier output. When light is incident on the photodiode the output pin transitions in a
OUT– 11 O
negative direction from the no light condition (APD anode connected to negative bias).
Noninverting amplifier output. When light is incident on the photodiode the output pin transitions in a
OUT+ 10 O
positive direction from the no light condition (APD anode connected to negative bias).
VDD1 2 I Positive power supply for the transimpedance amplifier stage.
Positive power supply for the differential amplifier stage. Tie VDD1 and VDD2 to the same power
VDD2 14 I
supply with independent power-supply bypassing.
VOCM 12 I Differential amplifier common-mode output setting.
VOD 9 I Differential amplifier differential output offset setting.
Thermal pad — Connect the thermal pad to GND or the most negative power supply of the device under test (DUT).

(1) TI recommends driving a digital pin with a low-impedance source rather than leaving the pin floating because fast-moving transients
can couple into the pin and inadvertently change the logic level.
(2) I = input, O = output

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DIE THICKNESS BACKSIDE FINISH BACKSIDE POTENTIAL BOND PAD

METALLIZATION
381 μm Silicon with backgrind Wafer backside is not electrically isolated and should be held AlCu
at the same potential as the most negative power supply
connected to the die (GND)

40

LMH
17 16 15 14 32401

13
1 PAD#1

12
2

1060
11
3
10

4
9

5 6 7 8
0

0 40
1025

Figure 5-2. Bare Die Package

Table 5-2. Bond Pad Coordinates of Bare Die Version in Microns

PAD NUMBER PAD NAME X-MIN Y-MIN X-MAX Y-MAX
1 GND 15 711.4 90 786.4
2 VDD1 15 543 90 618
3 IN 15 362 90 437
4 NC 15 201 90 276
5 IDC_EN 124.675 15 199.675 90
6 EN 286.675 15 361.675 90
7 GND 547.7 15 622.7 90
8 NC 713.675 15 788.675 90
9 VOD 855 169.075 930 244.075
10 OUT+ 855 307.6 930 382.6
11 NC 855 452.5 930 527.5
12 OUT- 855 597.325 930 672.325
13 VOCM 855 736.05 930 811.05
14 NC 713.65 890 788.65 965
15 VDD2 547.675 890 622.675 965
16 NC 286.675 890 361.675 965
17 GAIN 124.675 890 199.675 965

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD1, VDD2 Total supply voltage, VDD (2) 3.65 V
Voltage at output pins 0 VDD V
Voltage at logic pins –0.25 VDD V
IIN Continuous current into IN 25 mA
IOUT Continuous output current 35 mA
TJ Junction temperature 150 °C
TA Operating free-air temperature –40 125 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) VDD1 and VDD2 should always be tied to the same supply and have separate power-supply bypass capacitors.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/
±1000
JEDEC JS-001, all pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC
±250
specification JESD22-C101, all pins(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Total supply voltage 3 3.3 3.45 V
TA Operating free-air temperature –40 125 °C

6.4 Thermal Information

LMH32401(2)
THERMAL METRIC(1) RGT (VQFN) UNIT
12 PINS
RθJA Junction-to-ambient thermal resistance 56.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 67 °C/W
RθJB Junction-to-board thermal resistance 31.3 °C/W
ΨJT Junction-to-top characterization parameter 3.7 °C/W
ΨJB Junction-to-board characterization parameter 31.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 15.6 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) Thermal information is applicable to packaged parts only.

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6.5 Electrical Characteristics: Gain = 2 kΩ

VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, GAIN = 0 V, IDC_EN = 3.3 V, RL = 100 Ω, and TA = 25℃
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 100 mVPP 450 MHz
LSBW Large-signal bandwidth VOUT = 1 VPP 450 MHz
tR, tF Rise and fall time VOUT = 100 mVPP, pulse width = 10 ns 0.8 ns
Slew rate(2) VOUT = 1 VPP, pulse width = 10 ns 1100 V/µs
Overload pulse extention (3) IIN = 10 mA, pulse width = 10 ns 4 ns
iN Integrated input current noise f = 500 MHz 250 nARMS
DC PERFORMANCE
Z21 Small-signal transimpedance gain(4) 1.75 2 2.25 kΩ
Differential output offset voltage
VOD –12 3.5 12 mV
(VOUT– – VOUT+)
ΔVOD/ΔTA Differential output offset voltage drift ±5.5 µV/°C
INPUT PERFORMANCE
RIN Input Resistance 60 100 120 Ω
VIN Default input bias voltage Input pin floating 2.42 2.47 2.52 V
ΔVIN/ΔTA Default input bias voltage drift Input pin floating 1.1 mV/°C
Z21 < 3-dB degradation from
IIN DC input current range 600 705 µA
IIN = 50 µA

(1) Input capacitance of photodiode.

(2) Average of rising and falling slew rate.
(3) Pulse width extension measured at 50% of pulse height of a square wave.
(4) Gain measured at the amplifier output pins when driving a 100-Ω resistive load. At higher resistor loads the gain increases.

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6.6 Electrical Characteristics: Gain = 20 kΩ

VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, GAIN = 3.3 V, IDC_EN = 3.3 V, RL = 100 Ω, and TA = 25℃
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 100 mVPP 275 MHz
LSBW Large-signal bandwidth VOUT = 1 VPP 275 MHz
tR, tF Rise and fall time VOUT = 100 mVPP, pulse width = 10 ns 1.3 ns
Slew rate(2) VOUT = 1 VPP, pulse width = 10 ns 700 V/µs
Overload pulse extension (4) IIN = 10 mA, pulse width = 10 ns 4 ns
iN Integrated input current noise f = 250 MHz 49 nARMS
DC PERFORMANCE
Z21 Small-signal transimpedance gain(3) 17 20 22.5 kΩ
Differential output offset voltage
VOD –20 5 20 mV
(VOUT– – VOUT+)
ΔVOD/ΔTA Differential output offset voltage ±17.5 µV/°C
INPUT PERFORMANCE
RIN Input Resistance 270 350 410 Ω
VIN Default input bias voltage Input pin floating 2.42 2.47 2.52 V
ΔVIN/ΔTA Default input bias voltage drift Input pin floating 1.1 mV/°C
Z21 < 3-dB degradation from
IIN DC input current range 60 72 µA
IIN = 5 µA

(1) Input capacitance of photodiode.

(2) Average of rising and falling slew rate.
(3) Gain measured at the amplifier output pins when driving a 100-Ω resistive load. At higher resistor loads the gain increases.
(4) Pulse width extension measured at 50% of pulse height of a square wave.

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6.7 Electrical Characteristics: Both Gains

VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, GAIN = 0 V / 3.3 V, IDC_EN = 3.3 V, RL = 100 Ω, and TA =
25℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT PERFORMANCE
Single-sided output voltage swing (high)
VOH (2) TA = 25°C 2.87 2.9 V

VOL Single-sided output voltage swing (low)(2) TA = 25°C 0.36 0.39 V

TA = 25°C, IIN = 500 µA, gain = 2 kΩ,
24 26.6 32
RL = 25 Ω
TA = –40°C, IIN = 500 µA, gain = 2 kΩ,
IOUT Linear output drive (sink and source) 27.1 mA
RL = 25 Ω
TA = 125°C, IIN = 500 µA, gain = 2 kΩ,
25.1
RL = 25 Ω
ISC Output short-circuit current (differential) (3) 70 mA
ZOUT DC output impedance (amplifier enabled) Differential impedance 18 21 24 Ω
ZOUT DC output impedance in shutdown Differential impedance 2.8 3.3 kΩ
OUTPUT COMMON-MODE CONTROL (VOCM) PERFORMANCE
SSBW Small-signal bandwidth VOCM = 100 mVPP at VOCM pin 285 MHz
LSBW Large-signal bandwidth VOCM = 1 VPP at VOCM pin 85 MHz
f = 10 MHz, 1-nF capacitor to GND on VOCM
eN Output common-mode noise 17.8 nV/√Hz
pin
Gain, (ΔVOCM/ΔVOCM) IN floating, VOCM = 1.1 V (driven) 1 V/V
AV TA = 25°C, VOCM = 0.7 V to 2.3 V –2% 0.5% 2%
Gain error
TA = –40°C to 125°C, VOCM = 0.7 V to 2.3 V ±1%
Input impedance 17 kΩ
VOCMOS VOCM pin default offset from 1.1 V VOCM floating, (VOCM measured - 1.1 V) 0 10 20 mV
ΔVOCM/
VOCM error vs Input current Gain = 20 kΩ, VOCM driven to 1.1 V –15 µV/µA
ΔIIN
Output common-mode voltage,
VOCM TA = 25°C, VOCM pin floating 1.05 1.1 1.15 V
(VOUT+ + VOUT-)/2
Output common-mode voltage drift,
TA = –40°C to 125°C, VOCM pin floating 75 µV/°C
(ΔVOCM/ΔTA)
Output common-mode voltage,
VOCM TA = 25°C, VOCM pin driven to 1.1 V 1.05 1.1 1.15 V
(VOUT+ + VOUT-)/2
Output common-mode voltage drift, TA = –40°C to 125°C,
–14 µV/°C
(ΔVOCM/ΔTA) VOCM pin driven to 1.1 V

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VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, GAIN = 0 V / 3.3 V, IDC_EN = 3.3 V, RL = 100 Ω, and TA =
25℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OUTPUT DIFFERENTIAL OFFSET (VOD) PERFORMANCE
SSBW Small-signal bandwidth VOD = 100 mVPP at VOD pin 45 MHz
LSBW Large-signal bandwidth VOD = 1 VPP 14 MHz
Differential output offset,
VOS_D IN floating, VOD = 0.5 V 490 510 530 mV
VOUT = (VOUT– –VOUT+)
Differential output offset drift, ΔVOS_D/ΔTA IN floating, VOD = 0.5 V 0.03 mV/℃
Differential output offset,
VOS_D IN floating, VOD floating 490 510 530 mV
VOUT = (VOUT– –VOUT+)
Differential output offset drift, ΔVOS_D/ΔTA IN floating, VOD floating 0.04 mV/℃
Gain, (ΔVOUT/ΔVOD), where
IN floating, VOCM = 1.1 V (driven) 1.01 V/V
VOUT = (VOUT– –VOUT+)
AV
TA = 25℃, VOD = 0 V to 1.2 V –5% –1% 5%
Gain error
TA = –40℃ to 125℃, VOD = 0 V to 1.2 V ±1.5%
Input impedance 2.5 kΩ
AMBIENT LIGHT CANCELLATION PERFORMANCE (IDC_EN = 0 V) (4)
IIN = 0 µA → 100 µA, GAIN = 2 kΩ 18
IIN = 0 µA → 10 µA, GAIN = 20 kΩ 2.5
Settling time (within VOD limit) µs
IIN = 100 µA → 0 µA, GAIN= 2 kΩ 35
IIN = 10 µA → 0 µA, GAIN = 20 kΩ 13
Differential output offset (VOUT– – VOUT+) shift
Ambient light current cancellation range 2 3 mA
from IDC = 10 µA < ±10 mV
POWER SUPPLY
TA = 25°C 24 30 33.5
IQ Quiescent current, total TA = 125°C 32 mA
TA = –40°C 27
Positive power-supply rejection ratio,
PSRR+ 54 66 dB
VDD1 = VDD2
SHUTDOWN
TA = 25°C 2.4 3.3 4.2
IQ Disabled quiescent current (EN = VDD) TA = –40°C 2.75 mA
TA = 125°C 5.2
Enable pin input bias current TA = 25°C 75 120 µA

(1) Input capacitance of photodiode.

(2) Output levels achieved by adjusting VOCM, VOD, and input current.
(3) Device cannot withstand continuous short-circuit between the differential outputs.
(4) Enabling the ambient light cancellation loop adds noise to the system.

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6.8 Electrical Characteristics: Logic Threshold and Switching Characteristics

VDD = 3.3 V, VOCM = Open, VOD = 0 V, CPD (1) = 1 pF, EN = 0 V, GAIN = 0 V / 3.3 V, IDC_EN = 3.3 V, RL = 100 Ω, and TA =
25℃. (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LOGIC THRESHOLD PERFORMANCE
High gain enable, threshold voltage Amplifier in high gain above this voltage 1.8 2 V
Low gain enable, threshold voltage Amplifier in low gain below this voltage 0.8 1 V
EN control, disable threshold voltage Amplifier disabled above this voltage 1.8 2 V
EN control, enable threshold voltage Amplifier enabled below this voltage 0.8 1 V
Ambient light cancellation loop disabled
IDC_EN control, disable threshold voltage 1.8 2 V
above this voltage
Ambient light cancellation loop enabled
IDC_EN control, enable threshold voltage 0.8 1 V
below this voltage
GAIN CONTROL TRANSIENT PERFORMANCE
High gain to low gain transition-time, Ambient loop disabled, fIN = 25 MHz,
90 ns
(1% settling) VOUT = 1 VPP (Initial condition), IDC = 0 µA
Low gain to high gain transition-time, Ambient loop disabled, fIN = 25 MHz,
750 ns
(1% settling) VOUT = 1 VPP (Final condition), IDC = 0 µA
Ambient loop enabled, fIN = 25 MHz,
High gain to low gain transition-time,
VOUT = 1 VPP (Initial condition), IDC = 100 4 µs
(1% settling)
µA
Low gain to high gain transition-time, Ambient loop enabled, fIN = 25 MHz,
4 µs
(1% settling) VOUT = 1 VPP (Final condition), IDC = 100 µA
EN CONTROL TRANSIENT PERFORMANCE
Ambient loop disabled, fIN = 25 MHz, VOUT
Enable transition-time (1% settling) 125 ns
= 1 VPP, IDC = 0 µA, GAIN = 2 kΩ
Ambient loop disabled, fIN = 25 MHz, VOUT
Disable transition-time (1% settling) 3 ns
= 1 VPP, IDC = 0 µA, GAIN = 2 kΩ
Ambient loop disabled, fIN = 25 MHz, VOUT
Enable transition-time (1% settling) 850 ns
= 1 VPP, IDC = 0 µA, GAIN = 20 kΩ
Ambient loop disabled, fIN = 25 MHz, VOUT
Disable transition-time (1% settling) 3 ns
= 1 VPP, IDC = 0 µA, GAIN = 20 kΩ
Ambient loop enabled, fIN = 25 MHz, VOUT =
Enable transition-time (1% settling) 10 µs
1 VPP, IDC = 100 µA, GAIN = 2 kΩ
Ambient loop enabled, fIN = 25 MHz, VOUT =
Disable transition-time (1% settling) 3.5 ns
1 VPP, IDC = 100 µA, GAIN = 20 kΩ
Ambient loop enabled, fIN = 25 MHz, VOUT =
Enable transition-time (1% settling) 4 µs
1 VPP, IDC = 100 µA, GAIN = 20 kΩ
Ambient loop enabled, fIN = 25 MHz, VOUT =
Disable transition-time (1% settling) 3 ns
1 VPP, IDC = 100 µA, GAIN = 2 kΩ

(1) Input capacitance of photodiode.

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6.9 Typical Characteristics

At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).

69 89

66 86
Transimpedance (dB:)

Transimpedance (dB:)
63 83

60 80

57 CIN = PCB only 77 CIN = PCB only

CIN = 0.5 pF CIN = 0.5 pF
CIN = 1 pF CIN = 1 pF
54 CIN = 2 pF 74 CIN = 2 pF
CIN = 4.7 pF CIN = 4.7 pF
CIN = 10 pF CIN = 10 pF
51 71
10M 100M 1G 10M 100M 1G
Frequency [Hz] Frequency [Hz]
Gain = 2 kΩ, VOUT = 100 mVPP Gain = 20 kΩ, VOUT = 100 mVPP
Figure 6-1. Small Signal Response vs Input Capacitance Figure 6-2. Small Signal Response vs Input Capacitance
69 89

66 86
Transimpedance (dB:)

Transimpedance (dB:)

63 83

60 80

57 CIN = PCB only 77 CIN = PCB only

CIN = 0.5 pF CIN = 0.5 pF
CIN = 1 pF CIN = 1 pF
54 CIN = 2 pF 74 CIN = 2 pF
CIN = 4.7 pF CIN = 4.7 pF
CIN = 10 pF CIN = 10 pF
51 71
10M 100M 1G 10M 100M 1G
Frequency [Hz] Frequency [Hz]
Gain = 2 kΩ, VOUT = 1 VPP Gain = 20 kΩ, VOUT = 1 VPP
Figure 6-3. Large Signal Response vs Input Capacitance Figure 6-4. Large Signal Response vs Input Capacitance
69 89

66 86
Transimpedance (dB:)

Transimpedance (dB:)

63 83

60 80

57 77

54 74
CIN = 0.5 pF, CLOAD = open CIN = 0.5 pF, CLOAD = open
CIN = 0.5 pF, CLOAD = 2.7 pF CIN = 0.5 pF, CLOAD = 2.7pF
51 71
10M 100M 1G 10M 100M 1G
Frequency [Hz] Frequency [Hz]
Gain = 2 kΩ, VOUT = 100 mVPP Gain = 20 kΩ, VOUT = 100 mVPP
Figure 6-5. Small Signal Response vs Load Capacitance Figure 6-6. Small Signal Response vs Load Capacitance

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6.9 Typical Characteristics (continued)

At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).

69 89

66 86
Transimpedance (dB:)

Transimpedance (dB:)
63 83

60 80

57 77
TA = 40qC TA = 40qC
54 TA = 25qC 74 TA = 25qC
TA = 85qC TA = 85qC
TA = 125qC TA = 125qC
51 71
10M 100M 1G 10M 100M 1G
Frequency [Hz] Frequency [Hz]
Gain = 2 kΩ, CIN = PCB Gain = 20 kΩ, CIN = PCB
Figure 6-7. Small Signal Response vs Ambient Temperature Figure 6-8. Small Signal Response vs Ambient Temperature
3 10k
Amplifier Enabled
Amplifier Disabled
Differential Output Impedance (:)

0
Transimpedance (dB:)

-3 1k

-6

-9 100

-12 ALC Disabled

ALC Enabled, Gain = 2 k:
ALC Enabled, Gain = 20 k:
-15 10
10k 100k 1M 10M 1M 10M 100M 1G
Frequency [Hz] Frequency (Hz)
IDC_IN = 100 µA Gain = 2 kΩ
Figure 6-9. Low-side Frequency Response vs Ambient Light Figure 6-10. Closed-loop Output Impedance vs Frequency
Cancellation
20 10
CPD = 0.5 pF CPD = 0.5 pF
CPD = 1 pF CPD = 1 pF
CPD = 2 pF CPD = 2 pF
CPD = 3 pF CPD = 3 pF
Input Noise (pA/—Hz)

Input Noise (pA/—Hz)

10

5 1
10k 100k 1M 10M 100M 1G 10k 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
Gain = 2 kΩ Gain = 20 kΩ
Figure 6-11. Input Noise Density vs Input Capacitance Figure 6-12. Input Noise Density vs Input Capacitance

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6.9 Typical Characteristics (continued)

At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).

20 5
CLOAD = open CLOAD = open
CLOAD = 2.7 pF CLOAD = 2.7 pF
Input Noise (pA/—Hz)

Input Noise (pA/—Hz)

10

5 1
10k 100k 1M 10M 100M 1G 10k 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
Gain = 2 kΩ Gain = 20 kΩ
Figure 6-13. Input Noise Density vs Load Capacitance Figure 6-14. Input Noise Density vs Load Capacitance
100 50
IDC = 0 PA IDC = 0 PA
IDC = 10 PA IDC = 10 PA
IDC = 100 PA IDC = 100 PA
IDC = 1 mA IDC = 1 mA
Input Noise (pA/—Hz)
Input Noise (pA/—Hz)

10

10

5 1
10k 100k 1M 10M 100M 1G 10k 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
Gain = 2 kΩ Gain = 20 kΩ
Figure 6-15. Input Noise Density vs Ambient Light DC Current Figure 6-16. Input Noise Density vs Ambient Light DC Current
10 200
TA = 125qC Differential Noise
TA = 25qC Single-Ended Noise
TA = 40qC
100
Output Noise (pA/—Hz)
Input Noise (pA/—Hz)

0.5 10
10k 100k 1M 10M 100M 1G 10k 100k 1M 10M 100M 1G
Frequency (Hz) Frequency (Hz)
Gain = 20 kΩ Gain = 20 kΩ
Figure 6-17. Input Noise Density vs Ambient Temperature Figure 6-18. Output Noise Density vs Output Configuration

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6.9 Typical Characteristics (continued)

At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).

1.75 1.75
0.1 VPP 0.1 VPP
1.5 1 VPP 1.5 1 VPP
Differential Output Voltage (V)

Differential Output Voltage (V)

1.5 VPP 1.5 VPP
1.25 1.25

1 1

0.75 0.75

0.5 0.5

0.25 0.25

0 0

-0.25 -0.25

Time (5 ns/div) Time (5 ns/div)

Gain = 2 kΩ Gain = 20 kΩ
Figure 6-19. Pulse Response vs Output Swing Figure 6-20. Pulse Response vs Output Swing
1.5 1.5
IIN = 500 PA IIN = 50 PA
1.25 IIN = 1 mA 1.25 IIN = 1 mA
Differential Output (V)

Differential Output (V)

1 1

0.75 0.75

0.5 0.5

0.25 0.25

0 0

-0.25 -0.25
Time (5 ns/div)
Time (5 ns/div)
Gain = 20 kΩ
Gain = 2 kΩ
Figure 6-22. Overloaded Pulse Response
Figure 6-21. Overloaded Pulse Response
3.5 3.5
EN EN
3 Differential Output 3 Differential Output
2.5 2.5

2 2
Voltage (V)

Voltage (V)

1.5 1.5

1 1

0.5 0.5

0 0

-0.5 -0.5

-1 -1
Time (25 ns/div) Time (25 ns/div)
Gain = 2 kΩ Gain = 20 kΩ
Figure 6-23. Turn-On Time Figure 6-24. Turn-On Time

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6.9 Typical Characteristics (continued)

At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).

3.5 3.5

3 3
Differential Output Voltage (V)

Differential Output Voltage (V)

2.5 2.5

2 2
EN EN
1.5 Differential Output 1.5 Differential Output
1 1

0.5 0.5

0 0

-0.5 -0.5

Time (1 ns/div) Time (1 ns/div)

Gain = 2 kΩ, VOD = 0.5 V Gain = 20 kΩ, VOD = 0.5 V
Figure 6-25. Turn-Off Time Figure 6-26. Turn-Off Time
0.15 0

0.125 -0.02
Differential Output Voltage (V)

Differential Output Voltage (V)

-0.04
0.1
-0.06
0.075
-0.08
0.05
-0.1
0.025
-0.12
0 -0.14

-0.025 -0.16

Time (5 Ps/div) Time (5 Ps/div)

Gain = 2 kΩ, IDC_IN = 0 µA → 100 µA 1 Gain = 2 kΩ, IDC_IN = 100 µA → 0 µA1
Figure 6-27. Ambient Loop Cancellation Settling Time Figure 6-28. Ambient Loop Cancellation Settling Time
1.6 0

1.4 -0.1
Differential Output Voltage (V)

Differential Output Voltage (V)

1.2
-0.2
1
-0.3
0.8
-0.4
0.6
-0.5
0.4
-0.6
0.2

0 -0.7

-0.2 -0.8

Time (1 Ps/div) Time (2 Ps/div)

Gain = 20 kΩ, IDC_IN = 0 µA → 100 µA1 Gain = 20 kΩ, IDC_IN = 100 µA → 0 µA1
Figure 6-29. Ambient Loop Cancellation Settling Time Figure 6-30. Ambient Loop Cancellation Settling Time

1 Current due to ambient light transitions at t = 0 in.

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6.9 Typical Characteristics (continued)

At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).

5 50
125 qC
-40 qC
25 qC
Gain (k:)

Gain (k:)
1 10

125 qC
-40 qC
25 qC
0.5 5
-1000 -750 -500 -250 0 250 500 750 1000 -100 -80 -60 -40 -20 0 20 40 60 80 100
Input Current (PA) Input Current (PA)
Gain = 2 kΩ, positive current is sinking current into the Gain = 20 kΩ, positive current is sinking current into the
photodiode's cathode photodiode's cathode
Figure 6-31. Transimpedance Gain vs Input Current Figure 6-32. Transimpedance Gain vs Input Current
2040 21000
Unit 1 Unit 1
Unit 2 Unit 2
Unit 3 20500 Unit 3
2020

20000
2000
Gain (:)
Gain (:)

19500

1980
19000

1960 18500

1940 18000
-40 -20 0 20 40 60 80 100 120 140 -40 -20 0 20 40 60 80 100 120 140
Temperature (qC) Temperature (qC)

Gain = 2 kΩ Gain = 20 kΩ

Figure 6-33. Transimpedance Gain vs Ambient Temperature Figure 6-34. Transimpedance Gain vs Ambient Temperature

2.5 2.6
2.25
2
2.55
Input Bias Voltage (V)

Input Bias Voltage (V)

1.75
1.5
1.25 2.5
1
0.75
2.45
0.5 Unit 1
0.25 Unit 2
Unit 3
0 2.4
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 -40 -20 0 20 40 60 80 100 120 140
Supply Voltage (V) Temperature (qC)
. Gain = 20 kΩ
Figure 6-35. Input Bias Voltage vs Supply Voltage Figure 6-36. Input Bias Voltage vs Ambient Temperature

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6.9 Typical Characteristics (continued)

At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).

34 35

30
Quiescent Current (mA)

Quiescent Current (mA)

32
25

20
30
15

10
28
Unit 1 125 qC
Unit 2 5 -40 qC
Unit 3 25 qC
26 0
-40 -20 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 2.5 3 3.5
Temperature (qC) Supply Voltage (V)
. .
Figure 6-37. Quiescent Current vs Ambient Temperature Figure 6-38. Quiescent Current vs Supply Voltage
1.8 1.2

1.7 1.1

1.6 1
Output Voltage (V)

Output Voltage (V)

1.5 0.9

1.4 Vout- (V) 0.8 Vout- (V)

Vout+ (V) Vout+ (V)
1.3 0.7

1.2 0.6

1.1 0.5

1 0.4
0 10 20 30 40 50 60 70 80 90 100 0 10 20 30 40 50 60 70 80 90 100
Input Current (PA) Input Current (PA)
VOD = 0.75 V, VOCM = 1.4 V VOD = 0.75 V, VOCM = 0.8 V
Figure 6-39. High-side Swing vs Input Current Figure 6-40. Low-side Swing vs Input Current
1.5 550
125 qC
Differential Output Offset Measured (V)

540 -40 qC
Differential Output Voltage (mV)

1.2 530 25 qC

520
0.9 510
500
0.6 490
480
0.3 470
460
0 450
0 0.3 0.6 0.9 1.2 1.5 1.8 2 0.5 1 1.5 2 2.5 3 3.5
Differential Output Offset Set (V) Input Current (mA)
. .
Figure 6-41. Differential Output Offset Gain Figure 6-42. Ambient Light Cancellation Range vs Ambient
Temperature

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6.9 Typical Characteristics (continued)

At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).

35 3500
125 qC
30 -40 qC 3000
25 qC
Quiescent Current (mA)

25 2500

Device Count
20 2000

15 1500

10 1000

5 500

0 0
0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3 3.3 25 26 27 28 29 30 31 32 33
Enable Voltage (EN) (V) Quiescent Current (mA)
Logic switching demonstrated using EN pin. IDC_EN and gain .
pins behave similarly. Figure 6-44. Quiescent Current Distribution
Figure 6-43. Logic Threshold vs Ambient Temperature
2500 3500

3000
2000
2500
Device Count
Device Count

1500
2000

1500
1000

1000
500
500

0 0
1750 1850 1950 2050 2150 2250 17500 18500 19500 20500 21500 22500
Gain (:) Gain (:)
. Gain = 20 kΩ
Figure 6-45. Transimpedance Gain (Low) Distribution Figure 6-46. Transimpedance Gain (High) Distribution
4500 3000

4000
2500
3500

3000 2000
Device Count

Device Count

2500
1500
2000

1500 1000

1000
500
500

0 0
1 1.05 1.1 1.15 1.2 1.25 450 460 470 480 490 500 510 520 530 540 550
Output Common Mode Voltage (V) Differential Output Voltage(mV)
. .
Figure 6-47. Output Common-Mode Voltage (VOCM) Distribution Figure 6-48. Differential Output Offset Voltage (VOD) Distribution

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6.9 Typical Characteristics (continued)

At VDD = 3.3 V, VOCM = open, VOD = 0 V, CPD = 1 pF, EN = 0 V (enabled), IDC_EN = 3.3 V (disabled), RL = 100 Ω (differential
load between OUT+ and OUT–), and TA = 25°C (unless otherwise noted).

2000 3000

2500
1500
2000
Device Count

Device Count
1000 1500

1000
500
500

0 0
17.5 18.25 19 19.75 20.5 21.25 22 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 4
Differential Output Impedance (:) Differential Output Impedance (k:)
Amplifier Enabled Amplifier Disabled
Figure 6-49. Differential Output Impedance (ZOUT) Distribution Figure 6-50. Differential Output Impedance (ZOUT) Distribution

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7 Detailed Description
7.1 Overview
The LMH32401 device is a single-channel, differential output, high-speed transimpedance amplifier (TIA) that
features several integrated functions geared towards light detection and ranging (LIDAR) and pulsed time-of-
flight (ToF) systems. The LMH32401 device is designed to work with photodiode (PD) configurations that
can source or sink the current. When the photodiode sinks the photocurrent (anode is biased to a negative
voltage and cathode is tied to the amplifier input) the fast recovery clamp activates when the amplifier input
is overloaded. When the photodiode sources the photocurrent (cathode is biased to a positive voltage and
anode is tied to the amplifier input) a soft clamp activates when the amplifier input is overloaded. When the soft
clamp activates, the amplifier takes longer to recover. The recovery time depends on the level of input overload.
The LMH32401 device is offered in a space-saving 3-mm × 3-mm, 16-pin VQFN package and is rated over a
temperature range from –40°C to +125°C.

7.2 Functional Block Diagram

GAIN VDD1 VDD2 EN

100 mA 1 k

Clamp

IDC + ISIG 10 k
IN Differential Output ADC Driver

ISIG R 2.4 × R 10 
TIA OUT

IDC +
Ambient Light
 VBIAS Cancellation –

IDC EN OUT+
VREF R 2.4 × R 10
VDD VDD
Voltage to Current
17 k 50.4 k
VOD VOCM
3 k 25 k

GND

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7.3 Feature Description

7.3.1 Switched Gain Transimpedance Amplifier
The LMH32401 device features a programmable gain transimpedance amplifier (TIA) stage followed by a
fixed-gain, single-ended input to differential output amplifier stage. The closed-loop bandwidth and noise of a
TIA are affected by the transimpedance gain and photodiode capacitance. For a given value of photodiode
capacitance, the LMH32401 device has higher bandwidth in its low-gain configuration compared to the high-gain
configuration. Increasing the gain of the TIA stage by a factor of X increases the output signal by a factor X, but
the noise contribution from the resistor only increases by √X. The input-referred noise density of the low-gain
configuration is therefore higher than the input-referred noise density of the high-gain configuration.
The gain of the TIA stage is controlled by the GAIN pin. Setting this pin low places the TIA in its low-gain
configuration, whereas setting the pin high places the TIA in a high-gain configuration. The LMH32401 device
defaults to its low-gain configuration when the GAIN pin is left floating.
7.3.2 Clamping and Input Protection
The LMH32401 device is designed to work with photodiode (PD) configurations that can source or sink current;
however, the LMH32401 is optimized for a sinking current configuration. It is assumed that the LMH32401 device
is being used with a PD that is configured with its cathode tied to the amplifier input and the anode tied to a
negative supply voltage, unless stated otherwise.
The LMH32401 features two internal clamps, a fast recovery clamp and a soft clamp. The fast recovery clamp
is the active clamp when the photodiode is sinking a photocurrent. The soft clamp is the active clamp when the
photodiode is sourcing a photocurrent. Stray reflections from nearby objects with high reflectivity can produce
large output current pulses from the PD. The linear input range of the LMH32401 device is approximately 65 µA
in the high-gain configuration and 650 µA in the low-gain configuration (PD sinking the photocurrent).
Input currents in excess of the linear current range cause the internal nodes of the amplifier to saturate, which
increases the amplifier recovery time. The end result is a broadening of the output pulse leading to blind zones in
the system response. To protect against this condition, the LMH32401 features an integrated clamp that absorbs
and diverts the excess current to the positive supply (VDD1) when the amplifier detects its nodes entering a
saturated condition. The integrated clamp minimizes the pulse extension to less than a few ns for input pulses
up to 100 mA. The power-supply pins (VDD1 and VDD2) must each have their own bypass capacitors to prevent
large input pulses from affecting the differential output stage. When the amplifier is in low-power mode, the
clamp circuitry is still active, thereby protecting the TIA input.
7.3.3 ESD Protection
All LMH32401 pins have an internal electrostatic discharge (ESD) protection diode to the positive and negative
supply rails to protect the amplifier from ESD events.
7.3.4 Differential Output Stage
The differential output stage of the LMH32401 device performs the following two functions, which are common
across all differential amplifiers:
1. Converts the single-ended output from the TIA stage to a differential output.
2. Performs a common-mode output shift to match the specified ADC input common-mode voltage.
The differential output stage has two 10-Ω series resistors on its output to isolate the amplifier output stage
transistors from the package bond-wire inductance and printed circuit board (PCB) capacitance. The net gain of
the LMH32401 device (TIA + output stage) is 2 kΩ (low gain) and 20 kΩ (high gain) when driving an external
100-Ω resistor. When the external load resistor is increased above 100 Ω, the effective gain from the IN pin to
the differential output pin increases. Conversely, when the external load resistor is decreased to less than 100
Ω, the effective gain from the IN pin to the differential output pin decreases as a result of the larger voltage drop
across the two internal 10-Ω resistors. When there is no load resistor between the OUT+ and OUT– pins, the
effective gain of the LMH32401 is 2.4 kΩ and 24 kΩ in the low-gain and high-gain configurations, respectively.

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The output common-mode voltage of the LMH32401 device can be set externally through the VOCM pin. A
resistor divider internal to the amplifier, between VDD2 and ground sets the default voltage to 1.1 V. The internal
resistors generate common-mode noise that is typically rejected by the CMRR of the subsequent ADC stage. To
maximize the amplifier signal-to-noise ratio (SNR), place an external noise bypass capacitor to ground on the
VOCM pin. In single-ended signal chains, such as ToF systems that use time-to-digital converters (TDCs), only
a single output of the LMH32401 device is needed. In such situations, terminate the unused differential output in
the same manner as the used output to maintain balance and symmetry. The signal swing of the single-ended
output is half the available differential output swing. Additionally, the common-mode noise of the output stage,
which is typically rejected by the differential input ADC, is now added to the total noise, further degrading SNR.
The output stage of the LMH32401 device has an additional VOD input that sets the differential output between
OUT– and OUT+. Figure 7-1 shows how each output pin of the LMH32401 device is at the voltage set by the
VOCM pin (default = 1.1 V) when the photodiode output current is zero and the VOD input is set to 0 V. When
the VOD pin is driven to a voltage of X volts, the two output pins are separated by X volts when the photodiode
current is zero. The average voltage is still equal to VOCM. For example, Figure 7-2 shows if VOCM is set to 1.1
V and VOD is set to 0.4 V, then OUT– = 1.1 V + 0.2 V = 1.3 V and OUT+ = 1.1 V – 0.2 V = 0.9 V.
The VOD pin is functional only when the LMH32401 device is used with a PD that sinks the photocurrent.
Set VOD = 0 V when the LMH32401 device is interfaced with a PD that sources the photocurrent. The VOD
output offset feature is included in the LMH32401 device because the output current of a photodiode is unipolar.
Depending on the reverse bias configuration, the photodiode can either sink or source current, but cannot do
both at the same time. With the anode connected to a negative bias and the cathode connected to the TIA
stage input, the photodiode can only sink current, which implies that the TIA stage output swings in a positive
direction above its default input bias voltage (2.47 V). Subsequently, OUT– only swings below VOCM and OUT+
only swings above VOCM. Figure 7-1 shows how the LMH32401 device only uses half of its output swing range
(VOUT = VOUT+ – VOUT–) when VOD = 0 V, because one output never swings below VOCM and the other output
never goes above VOCM. The signal dynamic range in this case is 0.4 VPP – 0 V = 0.4 VPP.
Figure 7-2 shows how the VOD pin voltage allows OUT– to be level-shifted above VOCM and OUT+ to be
level-shifted below VOCM to maximize the output swing capabilities of the amplifier. The signal dynamic range in
this case is 0.4 VPP – (–0.4 VPP) = 0.8 VPP.

VOUT = 0.4 VPP VOUT = 0.4 VPP

VOUTí VOUTí
APD Excited APD Excited
1.3 V VOUT+
VOUT+ 1.3 V

VOCM = 1.1 V VOD = 0 V VOD = 0.4 V

VOCM = 1.1 V

0.9 V 0.9 V

VOUT = 0 VPP
No output from APD VOUT í0.4 VPP
Figure 7-1. Individual Single-Ended Outputs With No output from APD

VOD = 0 V Figure 7-2. Individual Single-Ended Outputs With

VOD = 0.4 V

When the LMH32401 device drives a 100-Ω load, the voltage set at the VOD pin is equal to the differential
output offset (VOUT = VOUT+ – VOUT–) when the input signal current is zero. Use Equation 1 to calculate the
differential output offset under other load conditions.

RL
V OD 1.2 u VOD u
R L u 20 : (1)

Where:
• VOD = Voltage applied at pin 9
• VOD = (VOUT– – VOUT+)
• RL = External load resistance

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7.4 Device Functional Modes

7.4.1 Ambient Light Cancellation (ALC) Mode
The LMH32401 device has an integrated DC cancellation loop that cancels and voltage offsets from incidental
ambient light. The ALC mode only works when the PD is sinking the photocurrent. The DC cancellation loop is
enabled by setting IDC_EN low. Incident ambient light on a photodiode produces a DC current resulting in an
offset voltage at the output of the LMH32401's TIA stage. The Functional Block Diagram shows how the ALC
loop senses the low-frequency DC offset at the output of the TIA stage and compares it against an internal
reference voltage (VREF). The ALC loop then outputs an opposing DC current (IDC) to compensate for the
differential offset voltage at its input. The loop has a high-pass cutoff frequency of 100 kHz. The ambient light
cancellation loop is disabled when the amplifier is placed in power-down mode.
The shot noise current introduced by the DC cancellation loop increases the overall amplifier noise; so, if the
ambient light level is negligible, then disable the loop to improve SNR. The cancellation loop helps save PCB
space and system costs by eliminating the need for external AC coupling passive components. Additionally, the
extra trace inductance and PCB capacitance introduced by using external AC coupling components degrades
the LMH32401 device dynamic performance.
7.4.2 Power-Down Mode (Multiplexer Mode)
The LMH32401 device can be placed in low-power mode by setting EN high, which helps in saving system
power. Enabling low-power mode puts the outputs of the internal amplifiers in the LMH32401 device, including
the differential outputs, in a high-impedance state. Figure 7-3 shows how this device feature can further save
board space and cost by eliminating the need for a discrete high-speed multiplexer, if a system consists of
several photodiode and amplifier channels multiplexed to a single ADC channel. The disabled channel outputs
are not an ideal open circuit so as the number of multiplexed channels increases the disabled channels begin
to load the enabled channel. Multiplexing more than four channels in parallel degrades the performance of the
enabled channel. When the amplifier is in its low-power mode, the clamp circuitry is still active thereby protecting
the TIA input. The ambient light cancellation loop is disabled when the amplifier is placed in power-down mode.
When the LMH32401 device is brought out of power-down operation the ambient light cancellation loop requires
several time constants to settle. Figure 6-9 shows the low-frequency loop response which in turn determines the
time constant needed for the loop to settle.
1 NŸ DISABLED AMPLIFIER
100mA
Clamp
10 NŸ

TIA 10 Ÿ RISO
OUTí

í VBIAS Ambient Light +

Cancellation
±

OUT+
Output Offset 10 Ÿ RISO

RADC_IN

EN = 3.3 V CFILT VOCM ADC12QJ1600

1 NŸ RADC_IN
ENABLED AMPLIFIER
100mA
Clamp
10 NŸ

TIA 10 Ÿ RISO
OUTí

í VBIAS Ambient Light +

Cancellation
±

OUT+
Output Offset 10 Ÿ RISO

EN = 0 V

Figure 7-3. Configuring Two LMH32401 Devices in Multiplexer Mode to Drive a Single ADC

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The differential outputs of the LMH32401 device can directly drive a high-speed differential input ADC. Figure
8-1 shows the LMH32401 differential outputs directly driving the ADC12QJ1600. The effective signal gain
between the TIA input and the ADC input is 2 kΩ or 20 kΩ when driving an ADC with a 100-Ω differential input
impedance (RADC_IN = 50 Ω). Equation 2 gives the effective signal gain between the TIA input and the ADC input
when driving an ADC with any other value of differential input impedance (RADC_IN ≠ 50 Ω).
GAIN VDD1 VDD2

1 NŸ
100mA
Clamp
10 NŸ
IN Differential Output
ADC Driver

TIA 10 Ÿ OUTí

RADC_IN
í VBIAS Ambient Light +
Cancellation VOCM ADC12QJ1600
±
IDC EN RADC_IN

VOD Output Offset 10 Ÿ OUT+

GND EN

Figure 8-1. LMH32401 to ADC Interface

2 u R ADC _ IN
AV 2 k: or 20 k: u 1.2 u
2 u R ADC _ IN 20 : (2)

Where:
• AV = Differential gain from the TIA input to the ADC input
• RADC_IN = Input resistance of the ADC
Figure 8-2 shows a matching resistor network between the LMH32401 output and the ADC12QJ1600 input. The
matching network is needed to prevent signal reflections when the signal path between the LMH32401 and ADC
is very long. Equation 3 gives the effective gain from the TIA input to the ADC input when using a matching
resistor network.

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GAIN VDD1 VDD2

1 NŸ
100mA
Clamp
10 NŸ
IN Differential Output
ADC Driver

TIA 10 Ÿ RISO
OUTí
RADC_IN
í VBIAS Ambient Light +
Cancellation VOCM ADC12QJ1600
±
IDC EN RADC_IN
OUT+
VOD Output Offset 10 Ÿ RISO

GND EN

Figure 8-2. LMH32401 to ADC Interface with a Matching Resistor Network

2 u R ADC _ IN
AV 2 k: or 20 k: u 1.2 u
2 u R ADC _ IN 2 u R ISO 20 : (3)

Where:
• AV = Gain from the TIA input to the ADC input
• RADC_IN = Differential input resistance of the ADC
• RISO = Series resistance between the TIA and ADC
Equation 4 gives the voltage to be applied at the VOD pin (pin 9) if a certain differential offset voltage (VOD) is
needed at the ADC input for the circuit in Figure 8-2.

§ 1 · 2 u R ADC _ IN 2 u RISO 20 :
VOD V OD u ¨ ¸u
© 1.2 ¹ 2 u R ADC _ IN (4)

Where:
• VOD = Voltage applied at pin 9
• VOD = Desired differential offset voltage at the ADC input
• RADC_IN = Differential input resistance of the ADC
• RISO = Series resistance between the TIA and ADC
8.2 Typical Application
This section demonstrates the performance of the LMH32401 device when the input current flows into the IN
pin. Figure 8-3 shows the circuit used to test the LMH32401 device with a voltage source. This configuration
demonstrates the use case when the photodiode's anode is tied to the amplifier input and its cathode is tied to a
positive voltage greater than 2.47 V.

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GAIN VDD1 VDD2

100mA 1 NŸ
Clamp

2k 10 NŸ
IN Differential Output ADC Driver
50 measurement
ISIG R 2.4 × R 10 instrument
OUTí
50

CAPD
TIA
25 1 …F
+ IDC +
2.47 V Ambient Light CLOAD
± ±
Cancellation
25 1 …F
IDC EN GND
VREF R 2.4 × R 10 OUT+
VDD VDD
Voltage to Current
17 NŸ 50.4 NŸ
VOD VOCM
3 NŸ 25 NŸ

GND EN

Figure 8-3. LMH32401 Test Circuit

8.2.1 Design Requirements

The objective is to design a low-noise, wideband differential output transimpedance amplifier. The design
requirements are as follows:
• Amplifier supply voltage: 3.3 V
• Transimpedance gain: 2 kΩ and 20 kΩ
• Input capacitance: CPCB ≅ 1 pF
• Target bandwidth: > 250 MHz
• Differential output offset (VOD): 0 V
• Ambient light cancellation (IDC_EN): 3.3 V (disabled)
8.2.2 Detailed Design Procedure
Figure 8-3 shows the LMH32401 device test circuit used to measure its bandwidth and transient pulse response.
The voltage source is DC biased close to the input bias voltage of the LMH32401 device (approximately 2.47 V).
The internal design of the LMH32401 device is optimized to only source current out of the input pin (pin 3), and
all the data shown previously is with the current flowing out of the pin. When the voltage input from the source
exceeds 2.47 V, the LMH32401 device input will sink the current. Set VOD = 0 V when the input has to sink the
current from the photodiode, or in this case the voltage source. Set the DC bias so that sum of the input AC
and DC component is always greater than the input voltage (2.47 V) when testing the LMH32401 device with a
network analyzer or sinusoidal source.
Figure 8-4 and Figure 8-5 shows the bandwidth of the LMH32401 device when its input is sinking the current.
The input current range of the LMH32401 device is reduced when it is sinking the current. This effect is seen by
the decrease in bandwidth as the output swing increases and is more pronounced in a gain configuration of 20
kΩ. Compare Figure 8-4 with Figure 6-1 and Figure 6-3 to see the effect of current direction and input range in a
2 kΩ gain configuration. In a similar way, compare Figure 8-5 with Figure 6-2 and Figure 6-4 to see the effect of
current direction and input range in a gain of 20 kΩ.

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Figure 8-6 and Figure 8-7 show the pulsed output response of the LMH32401 device when the input current is
increased past the amplifier linear input range. When the input is sinking current, a soft clamp will aid in fast
recovery; however, the pulse will stretch slightly as the input current overrange increases. Compare Figure 8-6
with Figure 6-21 to see the pulse extension effect in a gain of 2 kΩ. Compare Figure 8-7 with Figure 6-22 to see
the pulse extension effect in a gain of 20 kΩ. Knowledge of the pulse extension can be used to determine the
approximate input current even under overrange situations that can occur due to the presence of retro-reflectors
in the environment. As shown in Figure 7-1, each half of the differential output pulse will only swing above or
below the VOCM voltage and the resulting maximum differential output swing is 0.75 VPP since VOD is set to 0
V. Consequently only half of the total ADC range is utilized in this photodiode configuration.
8.2.3 Application Curves

69 89

66 86
Transimpedance (dB:)

Transimpedance (dB:)
63 83

60 80

57 77

54 VOUT = 0.1 VPP 74 VOUT = 0.1 VPP

VOUT = 0.5 VPP VOUT = 0.5 VPP
VOUT = 1 VPP VOUT = 1 VPP
51 71
10M 100M 1G 10M 100M 1G
Frequency [Hz] Frequency [Hz]
Figure 8-4. Bandwidth vs Output Swing Figure 8-5. Bandwidth vs Output Swing
(Gain = 2 kΩ) (Gain = 20 kΩ)
1 1
IIN = 500 PA IIN = 50 PA
IIN = 1 mA IIN = 100 PA
0.75 IIN = 2.5 mA 0.75 IIN = 500 PA
IIN = 1 mA
Differential Output (V)

Differential Output (V)

0.5 0.5

0.25 0.25

0 0

-0.25 -0.25

Time (5 ns/div) Time (5 ns/div)

Figure 8-6. Pulse Response vs Input Current Figure 8-7. Pulse Response vs Input Current
(Gain = 2 kΩ) (Gain = 20 kΩ)

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9 Power Supply Recommendations

The LMH32401 device operates on 3.3-V supplies. The VDD1 and VDD2 pins must always be driven from
the same supply source and individually bypassed. A low power-supply source impedance must be maintained
across frequency. So use multiple bypass capacitors in parallel. Place the bypass capacitors as close to the
supply pins as possible. Place the smallest capacitor on the same side of the PCB as the LMH32401 device.
Placing the larger valued bypass capacitors on the same side of the PCB is preferable as well. However, if there
are space constraints, then the capacitors can be moved to the opposite side of the PCB using multiple vias to
reduce the series inductance resulting from the vias. The LMH32401 device can operate on bipolar supplies by
connecting pins 1 and 7 to the negative supply. The thermal pad must always be connected to the most negative
supply. The digital pin threshold voltages must be appropriately level shifted as they are connected to voltages at
pins 1 and 7.
10 Layout
10.1 Layout Guidelines
Achieving optimum performance with a high-frequency amplifier such as the LMH32401 device requires careful
attention to board layout parasitics and external component types. Recommendations that optimize performance
include the following:
• Minimize parasitic capacitance from the signal I/O pins to ac ground. Parasitic capacitance on the
output pins can cause instability whereas parasitic capacitance on the input pin reduces the amplifier
bandwidth. To reduce unwanted capacitance, cut out the power and ground traces under the signal input
and output pins. Otherwise, ground and power planes must be unbroken elsewhere on the board.
• Minimize the distance from the power-supply pins to high-frequency bypass capacitors. Use high-
quality, 100-pF to 0.1-µF, C0G and NPO-type decoupling capacitors with voltage ratings at least three times
greater than the amplifiers maximum power supplies. Place the smallest value capacitors on the same side
as the DUT. If space constraints force the larger value bypass capacitors to be placed on the opposite
side of the PCB, then use multiple vias on the supply and ground side of the capacitors. This configuration
makes sure that there is a low-impedance path to the amplifiers power-supply pins across the amplifiers gain
bandwidth specification. Avoid narrow power and ground traces to minimize inductance between the pins
and the decoupling capacitors. Larger (2.2-µF to 6.8-µF) decoupling capacitors that are effective at lower
frequency must be used on the supply pins. Place these decoupling capacitors further from the device. Share
the decoupling capacitors among several devices in the same area of the printed circuit board (PCB).

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10.2 Layout Example

GND
Place bypass capacitors close to VDD
and GND pins on the same side as
DUT. Use multiple vias to connect to
power and GND planes
16 15 14 13
GAIN NC VDD2 NC
Optional capacitor to reduce
GND VOCM noise from internal
1 12
VOCM resistors

GND
VDD1
2 11 Remove GND and Power
Remove GND and Power plane OUTí plane near output pins to
between IN and APD to minimize
Thermal Pad minimize parasitic PCB
parasitic capacitance
capacitance. Resistors to
IN further isolate parasitics
3 10
OUT+

Optional capacitor to reduce

NC 4 9 VOD noise from internal
VOD resistors
í VBIAS
GND
5 6 7 8
Optional isolation resistor to dampen
resonance due to bond wire IDC_EN EN GND NC
inductances and component
capacitances

Figure 10-1. Layout Recommendation

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11 Device and Documentation Support

11.1 Device Support
11.1.1 Development Support
• Texas Instruments, LMH32401 Transimpedance Amplifier Evaluation Module.
• Texas Instruments, Optical Front-End System Reference Design design guide.
• Texas Instruments, LIDAR-Pulsed Time-of-Flight Reference Design Using High-Speed Data Converters
design guide.
• Texas Instruments, LIDAR Pulsed Time of Flight Reference Design design guide.
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, LMH32401IRGT Evaluation Module user's guide.
• Texas Instruments, Transimpedance Considerations for High-Speed Amplifiers application report.
• Texas Instruments, What You Need To Know About Transimpedance Amplifiers – Part 1 blog.
• Texas Instruments, An Introduction to Automotive LIDAR.
• Texas Instruments, Maximizing the Dynamic Range of Analog Front Ends Having a Transimpedance
Amplifier.
• Texas Instruments, Time of Flight and LIDAR – Optical Front End Design.
• Texas Instruments, What You Need To Know About Transimpedance Amplifiers – Part 2 blog.
• Texas Instruments, Training Video: How to Design Transimpedance Amplifier Circuits.
• Texas Instruments, Training Video: High-Speed Transimpedance Amplifier Design Flow.
• Texas Instruments, Training Video: How to Convert a TINA-TI Model into a Generic SPICE Model.
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

11.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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Product Folder Links: LMH32401
 PACKAGE OPTION ADDENDUM

www.ti.com 21-Dec-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LMH32401IRGTR ACTIVE VQFN RGT 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 L32401 Samples

LMH32401IRGTT ACTIVE VQFN RGT 16 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 L32401 Samples

LMH32401YR ACTIVE DIESALE Y 0 3000 RoHS & Green Call TI N / A for Pkg Type -40 to 125 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 21-Dec-2022

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Sep-2023

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH32401IRGTR VQFN RGT 16 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
LMH32401IRGTT VQFN RGT 16 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2
LMH32401YR DIESALE Y 0 3000 180.0 8.4 1.1 1.1 0.4 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 26-Sep-2023

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH32401IRGTR VQFN RGT 16 3000 367.0 367.0 35.0
LMH32401IRGTT VQFN RGT 16 250 210.0 185.0 35.0
LMH32401YR DIESALE Y 0 3000 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
RGT0016C SCALE 3.600
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

3.1 B
A
2.9

PIN 1 INDEX AREA

3.1
2.9

SIDE WALL
METAL THICKNESS
DIM A
OPTION 1 OPTION 2
0.1 0.2
1.0 C
0.8

SEATING PLANE

0.05 0.08
0.00

1.68 0.07 (DIM A) TYP

5 8
EXPOSED
THERMAL PAD
12X 0.5 4
9

4X SYMM
1.5

1
12
0.30
16X
0.18
16 13 0.1 C A B
PIN 1 ID SYMM
(OPTIONAL) 0.05

0.5
16X
0.3

4222419/D 04/2022

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RGT0016C VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 1.68)
SYMM
16 13

16X (0.6)

1
12

16X (0.24)
SYMM

(2.8)
(0.58)
TYP
12X (0.5)
9
4

( 0.2) TYP
VIA

5 8
(R0.05) (0.58) TYP
ALL PAD CORNERS
(2.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:20X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

EXPOSED EXPOSED
METAL SOLDER MASK METAL METAL UNDER
OPENING SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4222419/D 04/2022

NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RGT0016C VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 1.55)
16 13

16X (0.6)

1
12

16X (0.24)

17 SYMM

(2.8)

12X (0.5)

9
4

METAL
ALL AROUND

5 8
SYMM
(R0.05) TYP

(2.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 17:

85% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:25X

4222419/D 04/2022

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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