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LMH6551
SNOSAK7D – FEBRUARY 2005 – REVISED JANUARY 2015

LMH6551 Differential, High-Speed Op Amp

1 Features 3 Description
•
1 370 MHz −3-dB Bandwidth (VOUT = 0.5 VPP) The LMH6551 device is a high-performance voltage
feedback differential amplifier and is part of the
• 50 MHz 0.1-dB Bandwidth LMH™ integrated circuits family of devices. The
• 2400 V/µs Slew Rate LMH6551 has the high speed and low distortion
• 18 ns Settling Time to 0.05% necessary for driving high-performance ADCs as well
• −94/−96 dB HD2/HD3 at 5 MHz as the current handling capability to drive signals over
balanced transmission lines like CAT 5 data cables.
The LMH6551 can handle a wide range of video and
2 Applications data formats.
• Differential AD Driver With external gain set resistors, the LMH6551 can be
• Video Over Twisted-Pair used at any desired gain. Gain flexibility coupled with
• Differential Line Driver high speed makes the LMH6551 suitable for use as
• Single End to Differential Converter an IF amplifier in high-performance communications
equipment.
• High-Speed Differential Signaling
The LMH6551 is available in the space-saving SOIC
• IF/RF Amplifier
and VSSOP packages.
• SAW Filter Buffer/Driver
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
SOIC (8) 4.90 mm × 3.91 mm
LMH6551
VSSOP (8) 3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.

4 Typical Application
RF
AV, RIN +
V
RS RG RO
VI
+ - IN-
VS VCM
a RT VO ADC
+ IN+
-
RG RO
RM -
V

RF

For R M  R G : DesignTarget:

VO RF 1
Av # 1) Set RT
VI RG 1 1

2RG (1  A v ) RS RIN
RIN # 2) Set RM RT ||RS
2  Av

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH6551
SNOSAK7D – FEBRUARY 2005 – REVISED JANUARY 2015 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 13
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 13
3 Description ............................................................. 1 9 Application and Implementation ........................ 14
4 Typical Application ................................................ 1 9.1 Application Information............................................ 14
9.2 Typical Applications ................................................ 14
5 Revision History..................................................... 2
6 Pin Configuration and Functions ......................... 3 10 Power Supply Recommendations ..................... 21
7 Specifications......................................................... 3 11 Layout................................................................... 22
11.1 Layout Guidelines ................................................. 22
7.1 Absolute Maximum Ratings ..................................... 3
11.2 Layout Example .................................................... 22
7.2 ESD Ratings.............................................................. 3
11.3 Power Dissipation ................................................. 23
7.3 Recommended Operating Conditions....................... 4
11.4 ESD Protection...................................................... 23
7.4 Thermal Information .................................................. 4
7.5 Electrical Characteristics: ±5 V ................................. 4 12 Device and Documentation Support ................. 24
7.6 Electrical Characteristics: 5 V (4)................................ 6 12.1 Documentation Support ........................................ 24
7.7 Electrical Characteristics: 3.3 V (4)............................. 7 12.2 Trademarks ........................................................... 24
7.8 Typical Performance Characteristics ........................ 9 12.3 Electrostatic Discharge Caution ............................ 24
12.4 Glossary ................................................................ 24
8 Detailed Description ............................................ 13
8.1 Overview ................................................................. 13 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram ....................................... 13
Information ........................................................... 24

5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (March 2013) to Revision D Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1

Changes from Revision B (March 2013) to Revision C Page

• Changed layout of National Data Sheet to TI format ........................................................................................................... 22

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6 Pin Configuration and Functions

D and DGK Package

8-Pin SOIC and VSSOP
Top View

1 8
-IN +IN

2 - + 7
VCM NC

3 6
V+ V-

4 5
+OUT -OUT

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
-IN 1 I Negative Input
VCM 2 I Output Common-Mode Voltage
V+ 3 P Positive Supply
+OUT 4 O Positive Output
-OUT 5 O Negative Output
V- 6 P Negative Supply
NC 7 — No Connection
+IN 8 I Positive Input

7 Specifications
(1) (2) (3)
7.1 Absolute Maximum Ratings
MIN MAX UNIT
Supply Voltage 13.2 V
Common-Mode Input Voltage ±Vs V
Maximum Input Current (pins 1, 2, 7, 8) 30 mA
(4)
Maximum Output Current (pins 4, 5) See
Maximum Junction Temperature 150 °C
Storage Temperature, Tstg −65 150 °C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate
conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the
Electrical Characteristics tables.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) For Soldering Information, see Product Folder at www.ti.com and SNOA549.
(4) The maximum output current (IOUT) is determined by device power dissipation limitations.

7.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2000
V(ESD) Electrostatic discharge V
Machine model (MM) ±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Operating Temperature Range −40 +125 °C
Total Supply Voltage 3 12 V

7.4 Thermal Information

LMH6551
THERMAL METRIC (1) D DGK UNIT
8 PINS 8 PINS
(2)
RθJA Junction-to-ambient thermal resistance 150 235 °C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is P D= (TJ(MAX) — TA)/ θJA. All numbers apply for package soldered directly into a 2 layer PC board with zero air flow.

7.5 Electrical Characteristics: ±5 V (1)

Single-ended in differential out, TA= 25°C, G = +1, VS = ±5 V, VCM = 0 V, RF = RG = 365 Ω, RL = 500 Ω; unless specified.
(2) (3) (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
AC PERFORMANCE (DIFFERENTIAL)
SSBW Small Signal −3 dB Bandwidth VOUT = 0.5 VPP 370 MHz
LSBW Large Signal −3 dB Bandwidth VOUT = 2 VPP 340 MHz
Large Signal −3 dB Bandwidth VOUT = 4 VPP 320 MHz
0.1 dB Bandwidth VOUT = 2 VPP 50 MHz
Slew Rate 4-V Step (4) 2400 V/μs
Rise/Fall Time 2-V Step 1.8 ns
Settling Time 2-V Step, 0.05% 18 ns
VCM PIN AC PERFORMANCE (COMMON-MODE FEEDBACK AMPLIFIER)
Common-Mode Small Signal VCMbypass capacitor removed 200 MHz
Bandwidth
DISTORTION AND NOISE RESPONSE
HD2 VO = 2 VPP, f = 5 MHz, RL=800 Ω −94 dBc
HD2 VO = 2 VPP, f = 20MHz, RL=800 Ω −85 dBc
HD3 VO = 2 VPP, f = 5 MHz, RL=800 Ω −96 dBc
HD3 VO = 2 VPP, f = 20 MHz, RL=800 Ω −72 dBc
en Input Referred Voltage Noise Freq ≥ 1 MHz 6.0 nV/√Hz
in Input Referred Noise Current Freq ≥ 1 MHz 1.5 pA/√Hz
INPUT CHARACTERISTICS (DIFFERENTIAL)
VOSD Input Offset Voltage Differential Mode, VID 0.5 ±4 mV
= 0, VCM = 0
At extreme ±6
temperatures
Input Offset Voltage Average −0.8 µV/°C
Temperature Drift (5)
IBI Input Bias Current (6) -4 0 µA
-10
Input Bias Current Average −2.6 nA/°C
Temperature Drift (5)

(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods.
(3) Typical numbers are the most likely parametric norm.
(4) Slew Rate is the average of the rising and falling edges.
(5) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(6) Negative input current implies current flowing out of the device.
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Electrical Characteristics: ±5 V(1) (continued)

Single-ended in differential out, TA= 25°C, G = +1, VS = ±5 V, VCM = 0 V, RF = RG = 365 Ω, RL = 500 Ω; unless specified.
(2) (3) (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Input Bias Difference Difference in Bias currents between the 0.03 µA
two inputs
CMRR Common-Mode Rejection Ratio DC, VCM = 0 V, VID = 0 V 72 80 dBc
RIN Input Resistance Differential 5 MΩ
CIN Input Capacitance Differential 1 pF
CMVR Input Common-Mode Voltage Range CMRR > 53dB +3.1 +3.2
V
−4.6 −4.7
VCMPIN INPUT CHARACTERISTICS (COMMON-MODE FEEDBACK AMPLIFIER)
VOSC Input Offset Voltage Common Mode, VID = 0.5 ±5 mV
0
At extreme ±8
temperatures
Input Offset Voltage Average 8.2 µV/°C
Temperature Drift (5)
Input Bias Current (6) −2 μA
VCM CMRR VID = 0 V, 1-V step on VCM pin, measure 70 75 dB
VOD
Input Resistance 25 kΩ
Common-Mode Gain ΔVO,CM/ΔVCM 0.995 0.999 1.005 V/V
OUTPUT PERFORMANCE
Output Voltage Swing Single-Ended, Peak to ±7.38 ±7.8 V
Peak
At extreme ±7.18
temperatures
Output Common-Mode Voltage VID = 0 V, ±3.69 ±3.8 V
Range
IOUT Linear Output Current VOUT = 0V ±50 ±65 mA
ISC Short Circuit Current Output Shorted to Ground 140 mA
VIN = 3-V Single-Ended (7)l
Output Balance Error ΔVOUTCommon Mode −70 dB
/ΔVOUTDIfferential , VOUT = 0.5 Vpp
Differential, f = 10 MHz
MISCELLANEOUS PERFORMANCE
AVOL Open Loop Gain Differential 70 dB
PSRR Power Supply Rejection Ratio DC, ΔVS = ±1 V 74 90 dB
Supply Current RL = ∞ 11 12.5 14.5 mA
At extreme 16.5
temperatures

(7) The maximum output current (IOUT) is determined by device power dissipation limitations.

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7.6 Electrical Characteristics: 5 V (1)

Single-ended in differential out, TA= 25°C, G = +1, VS = 5 V, VCM = 2.5 V, RF = RG = 365 Ω, RL = 500 Ω; unless specified.
(2) (3) (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SSBW Small Signal −3 dB Bandwidth RL = 500 Ω, VOUT = 0.5 VPP 350 MHz
LSBW Large Signal −3 dB Bandwidth RL = 500 Ω, VOUT = 2 VPP 300 MHz
0.1 dB Bandwidth VOUT = 2 VPP 50 MHz
Slew Rate 4-V Step (4) 1800 V/μs
Rise/Fall Time, 10% to 90% 4-V Step 2 ns
Settling Time 4-V Step, 0.05% 17 ns
VCM PIN AC PERFORMANCE (COMMON-MODE FEEDBACK AMPLIFIER)
Common-Mode Small Signal 170 MHz
Bandwidth
DISTORTION AND NOISE RESPONSE
HD2 2nd Harmonic Distortion VO = 2 VPP, f = 5 MHz, RL=800 Ω −84 dBc
HD2 VO = 2 VPP, f = 20 MHz, RL=800 Ω −69 dBc
HD3 3rd Harmonic Distortion VO = 2 VPP, f = 5 MHz, RL=800 Ω −93 dBc
HD3 VO = 2 VPP, f = 20 MHz, RL=800 Ω −67 dBc
en Input Referred Noise Voltage Freq ≥ 1 MHz 6.0 nV/√Hz
in Input Referred Noise Current Freq ≥ 1 MHz 1.5 pA/√Hz
INPUT CHARACTERISTICS (DIFFERENTIAL)
VOSD Input Offset Voltage Differential Mode, VID = 0.5 ±4 mV
0, VCM = 0
At extreme ±6
temperatures
Input Offset Voltage Average −0.8 µV/°C
Temperature Drift (5)
IBIAS Input Bias Current (6) −4 0 μA
-10
Input Bias Current Average −3 nA/°C
Temperature Drift (5)
Input Bias Current Difference Difference in Bias currents between the 0.03 µA
two inputs
CMRR Common-Mode Rejection Ratio DC, VID = 0 V 70 78 dBc
Input Resistance Differential 5 MΩ
Input Capacitance Differential 1 pF
VICM Input Common-Mode Range CMRR > 53 dB +3.1 +3.2
+0.4 +0.3
VCMPIN INPUT CHARACTERISTICS (COMMON-MODE FEEDBACK AMPLIFIER)
Input Offset Voltage Common Mode, VID = 0.5 ±5 mV
0
At extreme ±8
temperatures
Input Offset Voltage Average 5.8 µV/°C
Temperature Drift
Input Bias Current 3 μA
VCM CMRR VID = 0, 70 75 dB
1V step on VCM pin, measure VOD
Input Resistance VCM pin to ground 25 kΩ

(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods.
(3) Typical numbers are the most likely parametric norm.
(4) Slew Rate is the average of the rising and falling edges.
(5) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(6) Negative input current implies current flowing out of the device.
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Electrical Characteristics: 5 V(1) (continued)

Single-ended in differential out, TA= 25°C, G = +1, VS = 5 V, VCM = 2.5 V, RF = RG = 365 Ω, RL = 500 Ω; unless specified.
(2) (3) (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Common-Mode Gain ΔVO,CM/ΔVCM 0.995 0.991 1.005 V/V
OUTPUT PERFORMANCE
VOUT Output Voltage Swing Single-Ended, Peak to Peak, VS= ±2.5 ±2.4 ±2.8 V
V, VCM= 0 V
IOUT Linear Output Current VOUT = 0-V Differential ±45 ±60 mA
ISC Output Short Circuit Current Output Shorted to Ground 230 mA
VIN = 3-V Single-Ended (7)
CMVR Output Common-Mode Voltage VID = 0, VCMpin = 1.2 V and 3.8 V 3.72 3.8
V
Range 1.23 1.2
Output Balance Error ΔVOUTCommon Mode −65 dB
/ΔVOUTDIfferential, VOUT = 1Vpp
Differential, f = 10 MHz
MISCELLANEOUS PERFORMANCE
Open Loop Gain DC, Differential 70 dB
PSRR Power Supply Rejection Ratio DC, ΔVS = ±0.5 V 72 88 dB
IS Supply Current RL = ∞ 10 11.5 13.5 mA
At extreme 15.5
temperatures

(7) The maximum output current (IOUT) is determined by device power dissipation limitations.

7.7 Electrical Characteristics: 3.3 V (1)

Single-ended in differential out, TA= 25°C, G = +1, VS = 3.3 V, VCM = 1.65 V, RF = RG = 365 Ω, RL = 500 Ω; unless specified.
(2) (3) (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SSBW Small Signal −3 dB Bandwidth RL = 500 Ω, VOUT = 0.5 VPP 320 MHz
LSBW Large Signal −3 dB Bandwidth RL = 500 Ω, VOUT = 1 VPP 300 MHz
Slew Rate 1-V Step (4) 700 V/μs
Rise/Fall Time, 10% to 90% 1-V Step 2 ns
VCM PIN AC PERFORMANCE (COMMON-MODE FEEDBACK AMPLIFIER)
Common-Mode Small Signal 95 MHz
Bandwidth
DISTORTION AND NOISE RESPONSE
HD2 2nd Harmonic Distortion VO = 1 VPP, f = 5 MHz, RL=800 Ω −93 dBc
HD2 VO = 1 VPP, f = 20 MHz, RL=800 Ω −74 dBc
HD3 3rd Harmonic Distortion VO = 1 VPP, f = 5 MHz, RL=800 Ω −85 dBc
HD3 VO = 1 VPP, f = 20 MHz, RL=800 Ω −69 dBc

(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
(2) Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods.
(3) Typical numbers are the most likely parametric norm.
(4) Slew Rate is the average of the rising and falling edges.

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Electrical Characteristics: 3.3 V(1) (continued)

Single-ended in differential out, TA= 25°C, G = +1, VS = 3.3 V, VCM = 1.65 V, RF = RG = 365 Ω, RL = 500 Ω; unless specified.
(2) (3) (2)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT CHARACTERISTICS (DIFFERENTIAL)
VOSD Input Offset Voltage Differential Mode, VID = 0, VCM = 0 1 mV
Input Offset Voltage Average 1.6 µV/°C
Temperature Drift (5)
IBIAS Input Bias Current (6) −8 μA
Input Bias Current Average 9.5 nA/°C
Temperature Drift (5)
Input Bias Current Difference Difference in Bias currents between the 0.3 µA
two inputs
CMRR Common-Mode Rejection Ratio DC, VID = 0 V 78 dBc
Input Resistance Differential 5 MΩ
Input Capacitance Differential 1 pF
VICM Input Common-Mode Range CMRR > 53 dB +1.5
+0.3
VCMPIN INPUT CHARACTERISTICS (COMMON-MODE FEEDBACK AMPLIFIER)
Input Offset Voltage Common Mode, VID = 0 1 ±5 mV
Input Offset Voltage Average 18.6 µV/°C
Temperature Drift
Input Bias Current 3 μA
VCM CMRR VID = 0, 60 dB
1-V step on VCM pin, measure VOD
Input Resistance VCM pin to ground 25 kΩ
Common-Mode Gain ΔVO,CM/ΔVCM 0.999 V/V
OUTPUT PERFORMANCE
VOUT Output Voltage Swing Single-Ended, Peak to Peak, VS= 3.3 V, ±0.75 ±0.9 V
VCM= 1.65 V
IOUT Linear Output Current VOUT = 0-V Differential ±30 ±40 mA
ISC Output Short Circuit Current Output Shorted to Ground 200 mA
VIN = 2-V Single-Ended (7)
CMVR Output Common-Mode Voltage VID = 0, VCMpin = 1.2 V and 2.1 V 2.1
V
Range 1.2
Output Balance Error ΔVOUTCommon Mode /ΔVOUTDIfferential, −65 dB
VOUT = 1-Vpp Differential, f = 10 MHz
MISCELLANEOUS PERFORMANCE
Open Loop Gain DC, Differential 70 dB
PSRR Power Supply Rejection Ratio DC, ΔVS = ±0.5 V 75 dB
IS Supply Current RL = ∞ 8 mA

(5) Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
(6) Negative input current implies current flowing out of the device.
(7) The maximum output current (IOUT) is determined by device power dissipation limitations.

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7.8 Typical Performance Characteristics

(TA = 25°C, VS = ±5 V, RL = 500 Ω, RF = RG = 365 Ω; Unless Specified).

2 2
1 1
0 0
-1 -1
VOD = 2 VPP VOD = 2 VPP
-2 -2
GAIN (dB)

GAIN (dB)
-3 -3
VOD = 0.5 VPP
-4 -4
VOD = 0.5 VPP
-5 -5
-6 -6
SINGLE ENDED INPUT SINGLE ENDED INPUT
-7 VS = ±5V -7 VS = 5V
-8 -8
1 10 100 1000 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 1. Frequency Response vs Supply Voltage Figure 2. Frequency Response

2 70
1
60
0

SUGGESTED RO (:)
-1 50
VOD = 1 VPP
-2
GAIN (dB)

40
-3
VOD = 0.5 VPP
-4 30

-5
20
-6
SINGLE ENDED INPUT LOAD = 1 k: || CAP LOAD
10
-7 VS = 3.3V VS = 5V
-8 0
1 10 100 1000 1 10 100
FREQUENCY (MHz)
CAPACITIVE LOAD (pF)
Figure 3. Frequency Response vs VOUT Figure 4. Suggested ROUT vs Cap Load
0.8 2.5
2
0.6
1.5
VOUT DIFFERENTIAL (V)
VOUT DIFFERENTIAL (V)

0.4
1
0.2 0.5
0 0

-0.2 -0.5
-1 VS = 5V
-0.4 VS = 3.3V
-1.5 RL = 500:
RL = 500:
-0.6 RF = 360:
RF = 360: -2
-0.8 -2.5
0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50

TIME (ns) TIME (ns)

Figure 5. 1 VPP Pulse Response Single-Ended Input Figure 6. 2 VPP Pulse Response Single-Ended Input

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Typical Performance Characteristics (continued)

(TA = 25°C, VS = ±5 V, RL = 500 Ω, RF = RG = 365 Ω; Unless Specified).
3 0.12
VS = ±5V
0.1
2 RL = 500:
0.08

COMMON MODE VOUT (V)

RF = 360:
VOUT DIFFERENTIAL (V)

0.06 VOUT = 4 VPP

1
0.04
0 0.02
0
-1
VS = ±5V -0.02

RL = 500: -0.04
-2
RF = 360: -0.06
-3 -0.08
0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50

TIME (ns) TIME (ns)

Figure 7. Large Signal Pulse Response Figure 8. Output Common-Mode Pulse Response
-50 -50
VS = ±5V HD3 VS = 5V HD3

-60 VOUT = 2 VPP VOUT = 2 VPP

VCM = 0V -60 VCM = 2.5V

DISTORTION (dBc)
DISTORTION (dBc)

RL = 800: RL = 800:
-70
-70
-80
-80
-90
HD2
HD2 -90
-100

-110 -100
0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 30 35 40

FREQUENCY (MHz) FREQUENCY (MHz)

Figure 9. Distortion vs Frequency Figure 10. Distortion vs Frequency

-50 -30
VS = 3.3V VOUT = 2 VPP
VOUT = 1 VPP HD3 -40 f = 5 MHz
-60 VCM = 1.65V VCM = VS/2
-50
DISTORTION (dBc)

DISTORTION (dBc)

RL = 800:
-70
-60

-80 -70
HD3
-80
HD2
-90
-90
HD2
-100 -100
0 5 10 15 20 25 30 35 40 3 4 5 6

FREQUENCY (MHz) SUPPLY VOLTAGE (V)

Figure 11. Distortion vs Frequency Figure 12. Distortion vs Supply Voltage (Split Supplies)

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Typical Performance Characteristics (continued)

(TA = 25°C, VS = ±5 V, RL = 500 Ω, RF = RG = 365 Ω; Unless Specified).
-60 4
VOUT = 4 VPP
-65 3.9
f = 5 MHz
VCM = 0V 3.8
-70
DISTORTION (dBc)

3.7

MAXIMUM VOUT (V)

HD3
-75
3.6
-80 3.5

-85 3.4
HD2 VIN = 3.88V SINGLE ENDED
3.3
-90 VS = ±5V
3.2
-95 AV = 2
3.1
RF = 730:
-100 3
6 7 8 9 10 11 12 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100
SUPPLY VOLTAGE (V) OUTPUT CURRENT (mA)
Figure 13. Distortion vs Supply Voltage (Single Supply) Figure 14. Maximum VOUT vs IOUT
-3 100
VIN = 3.88V SINGLE ENDED VS = ±5V
-3.1
VS = ±5V VIN = 0V
-3.2 AV = 2 10
MINIMUM VOUT (V)

-3.3 RF = 730:
-3.4
-3.5 |Z| (:) 1

-3.6

-3.7
0.1
-3.8

-3.9
-4 0.01
0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 100 1000
OUTPUT CURRENT (mA) FREQUENCY (MHz)

Figure 15. Minimum VOUT vs IOUT Figure 16. Closed-Loop Output Impedance
100 100
VS = 5V VS = 3.3V
VIN = 0V VIN = 0V

10 10
|Z| (:)

|Z| (:)

1 1

0.1 0.1

0.01 0.01
0.01 0.1 1 10 100 1000 0.01 0.1 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 17. Closed-Loop Output Impedance Figure 18. Closed-Loop Output Impedance

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Typical Performance Characteristics (continued)

(TA = 25°C, VS = ±5 V, RL = 500 Ω, RF = RG = 365 Ω; Unless Specified).
100 100
90 90
PSRR +
PSRR (dBc DIFFERENTIAL)

PSRR (dBc DIFFERENTIAL)

80 80

70 70
60 60
PSRR -
50 50
40 40
30 30
VS = ±5V VS = +5V
20 RL = 200: 20 RL = 200:
10 VCM = 0V 10 VCM = 2.5V
0 0
0.01 0.1 1 10 100 1000 0.01 0.1 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 19. PSRR Figure 20. PSRR

80 -25
-30 VS = ±5V
75 RF = 360:
-35
RL = 500:

BALANCE ERROR (dBc)

70 -40
-45 VIN = 0.5 VPP
65 -50
CMRR (dB)

-55
60
-60
55 -65
-70
50 -75
VIN, CM = 0.5 VPP -80
45
VS = ±5V -85
40 -90
0.1 1 10 100 1000 1 10 100 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 21. CMRR Figure 22. Balance Error

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8 Detailed Description

8.1 Overview
The LMH6551 is a fully differential amplifier designed to provide low distortion amplification to wide bandwidth
differential signals. The LMH6551, though fully integrated for ultimate balance and distortion performance,
functionally provides three channels. Two of these channels are the V+ and V− signal path channels, which
function similarly to inverting mode operational amplifiers and are the primary signal paths. The third channel is
the common-mode feedback circuit. This is the circuit that sets the output common mode as well as driving the
V+ and V− outputs to be equal magnitude and opposite phase, even when only one of the two input channels is
driven. The common-mode feedback circuit allows single-ended to differential operation.

8.2 Functional Block Diagram

V+

+OUT
-IN ±
2.5 k
High-Aol +
Differential I/O
Amplifier ±
2.5 k
+IN +
-OUT

V+
50 k

±
Vcm
Error
Amplifier
+ Vcm

50 k

V±

8.3 Feature Description

The LMH6551 combines a core differential I/O, high-gain block with an output common-mode sense that is
compared to a reference voltage and then fed back into the main amplifier block to control the average output to
that reference. The differential I/O block is a classic, high open-loop gain stage. The high-speed differential
outputs include an internal averaging resistor network to sense the output common-mode voltage. This voltage is
compared by a separate VCM error amplifier to the voltage on the VOCM pin. If floated, this reference is at half
the total supply voltage across the device using two 50-kΩ resistors. This VCM error amplifier transmits a
correction signal into the main amplifier to force the output average voltage to meet the target voltage on the
VOCM pin.

8.4 Device Functional Modes

This wideband FDA requires external resistors for correct signal-path operation. When configured for the desired
input impedance and gain setting with these external resistors, the amplifier can be either on with the PD pin
asserted to a voltage greater than Vs– + 1.7 V, or turned off by asserting PD low. Disabling the amplifier shuts
off the quiescent current and stops correct amplifier operation. The signal path is still present for the source
signal through the external resistors. The VOCM control pin sets the output average voltage. Left open, VOCM
defaults to an internal midsupply value. Driving this high-impedance input with a voltage reference within its valid
range sets a target for the internal VCM error amplifier.

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The LMH6551 is a fully differential amplifier designed to provide low distortion amplification to wide bandwidth
differential signals. The LMH6551, though fully integrated for ultimate balance and distortion performance,
functionally provides three channels. Two of these channels are the V+ and V− signal path channels, which
function similarly to inverting mode operational amplifiers and are the primary signal paths. The third channel is
the common-mode feedback circuit. This is the circuit that sets the output common mode as well as driving the
V+ and V− outputs to be equal magnitude and opposite phase, even when only one of the two input channels is
driven. The common-mode feedback circuit allows single-ended to differential operation.
The LMH6551 is a voltage feedback amplifier with gain set by external resistors. Output common-mode voltage
is set by the VCM pin. This pin should be driven by a low impedance reference and should be bypassed to ground
with a 0.1 µF ceramic capacitor. Any signal coupling into the VCM will be passed along to the output and will
reduce the dynamic range of the amplifier.

9.2 Typical Applications

9.2.1 Typical Fully Differential Application

RF1
RO

RG1
+
CL RL VO
VCM
VI a
-
RG2

RO
RF2

Figure 23. Typical Fully Differential Application Schematic

9.2.1.1 Design Requirements

Applications using fully differential amplifiers have several requirements. The main requirements are high linearity
and good signal amplitude. Linearity is accomplished by using well matched feedback and gain set resistors as
well as an appropriate supply voltage. The signal amplitude can be tailored by using an appropriate gain. In this
design, the gain is set for a gain of 2 (Rf=500/ RG=250) and the distortion criteria is better than -90 dBc at a
frequency of 5 Mhz for HD2 and HD3. The supply voltage is set for ±5 V and the output common mode is 0 V.

9.2.1.2 Detailed Design Procedure

9.2.1.2.1 Fully Differential Operation

The LMH6551 will perform best when used with split supplies and in a fully differential configuration. See
Figure 23 and Figure 24 for recommend circuits.

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Typical Applications (continued)

The circuit shown in Figure 23 is a typical fully differential application as might be used to drive an ADC. In this
circuit closed loop gain, (AV) = VOUT/ VIN = RF/RG. For all the applications in this data sheet VIN is presumed to be
the voltage presented to the circuit by the signal source. For differential signals this will be the difference of the
signals on each input (which will be double the magnitude of each individual signal), while in single-ended inputs
it will just be the driven input signal.
The resistors RO help keep the amplifier stable when presented with a load CL as is typical in an analog to digital
converter (ADC). When fed with a differential signal, the LMH6551 provides excellent distortion, balance and
common-mode rejection provided the resistors RF, RG and RO are well matched and strict symmetry is observed
in board layout. With a DC CMRR of over 80dB, the DC and low frequency CMRR of most circuits will be
dominated by the external resistors and board trace resistance. At higher frequencies board layout symmetry
becomes a factor as well. Precision resistors of at least 0.1% accuracy are recommended and careful board
layout will also be required.

500
50: 100:
TWISTED PAIR

250
+
2 VPP a VCM
-
250

2 VPP
50:
500
GAIN = 2

Figure 24. Fully Differential Cable Driver

With up to 15 VPP differential output voltage swing and 80 mA of linear drive current the LMH6551 makes an
excellent cable driver as shown in Figure 24. The LMH6551 is also suitable for driving differential cables from a
single-ended source.
The LMH6551 requires supply bypassing capacitors as shown in Figure 25 and Figure 26. The 0.01 µF and 0.1
µF capacitors should be leadless SMT ceramic capacitors and should be no more than 3 mm from the supply
pins. The SMT capacitors should be connected directly to a ground plane. Thin traces or small vias will reduce
the effectiveness of bypass capacitors. Also shown in both figures is a capacitor from the VCM pin to ground. The
VCM pin is a high impedance input to a buffer which sets the output common-mode voltage. Any noise on this
input is transferred directly to the output. Output common-mode noise will result in loss of dynamic range,
degraded CMRR, degraded Balance and higher distortion. The VCM pin should be bypassed even if the pin in not
used. There is an internal resistive divider on chip to set the output common-mode voltage to the mid point of the
supply pins. The impedance looking into this pin is approximately 25 kΩ. If a different output common-mode
voltage is desired drive this pin with a clean, accurate voltage reference.

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Typical Applications (continued)

+ +
V V
0.01 PF 0.01 PF

10 PF 0.01 PF 10 PF

+ +
VCM 0.1 PF
VCM
-
0.1 PF -
0.1 PF

10 PF 0.01 PF

-
V

Figure 25. Split Supply Bypassing Capacitors Figure 26. Single Supply Bypassing Capacitors

9.2.1.2.2 Capacitive Drive

As noted in Driving Analog-to-Digital Converters, capacitive loads should be isolated from the amplifier output
with small valued resistors. This is particularly the case when the load has a resistive component that is 500 Ω or
higher. A typical ADC has capacitive components of around 10 pF and the resistive component could be 1000 Ω
or higher. If driving a transmission line, such as 50-Ω coaxial or 100-Ω twisted pair, using matching resistors will
be sufficient to isolate any subsequent capacitance. For other applications see Figure 28 and Figure 4 in Typical
Performance Characteristics.

9.2.1.3 Application Curves

Many application circuits will have capacitive loading. As shown in Figure 4, amplifier bandwidth is reduced with
increasing capacitive load, so parasitic capacitance should be strictly limited.
In order to guarantee stability resistance should be added between the capacitive load and the amplifier output
pins. The value of the resistor is dependent on the amount of capacitive load as shown in Figure 5. This resistive
value is a suggestion. System testing will be required to determine the optimal value. Using a smaller resistor will
retain more system bandwidth at the expense of overshoot and ringing, while larger values of resistance will
reduce overshoot but will also reduce system bandwidth.

2 70
CL = 5.7 pF, ROUT = 60: VS = ±5V
1
60
0
CL = 10 pF, ROUT = 34:
SUGGESTED RO (:)

-1 50

-2
GAIN (dB)

CL = 27 pF, ROUT = 20: 40

-3
CL = 57 pF, ROUT = 15:
-4 30

-5 LOAD = (CL || 1 k:) IN

20
-6 SERIES WITH 2 ROUTS
10 LOAD = 1 k: || CAP LOAD
-7 VOUT = 0.5 VPP VS = ±5V
DIFFERENTIAL
-8 0
1 10 100 1000 1 10 100
FREQUENCY (MHz)
CAPACITIVE LOAD (pF)
Figure 27. Frequency Response vs Capacitive Load Figure 28. Suggested ROUT vs Cap Load

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Typical Applications (continued)

9.2.2 Single-Ended Input to Differential Output
The LMH6551 provides excellent performance as an active balun transformer. Figure 29 shows a typical
application where an LMH6551 is used to produce a differential signal from a single-ended source.
In single-ended input operation the output common-mode voltage is set by the VCM pin as in fully differential
mode. Also, in this mode the common-mode feedback circuit must recreate the signal that is not present on the
unused differential input pin. Figure 22 is the measurement of the effectiveness of this process. The common-
mode feedback circuit is responsible for ensuring balanced output with a single-ended input. Balance error is
defined as the amount of input signal that couples into the output common mode. It is measured as the
undesired output common-mode swing divided by the signal on the input. Balance error can be caused by either
a channel to channel gain error, or phase error. Either condition will produce a common-mode shift. Figure 22
measures the balance error with a single-ended input as that is the most demanding mode of operation for the
amplifier.
Supply and VCM pin bypassing are also critical in this mode of operation. See the above section on Fully
Differential Operation for bypassing recommendations and also see Figure 25 and Figure 26 for recommended
supply bypassing configurations.
RF
AV, RIN +
V
RS RG RO
VI VI1 VO1
+ - IN-
VS VCM
a RT VO ADC
+ IN+
- VO2
RG VI2 RO
RM -
+- V

RF

Conditions : Definitions :
RS RT ||RIN RG
1
RG  RF
RM RT || RS
RG  RM
2
RG  RM  RF
VO 2(1  1 5
Av # F for RM  RG
VI 1  2 5G

RG (1  2 )
2RG  RM (1  2 1 5G   $ v
RIN # for RM  RG
1  2   2   $v
VO1  VO2
VOCM VCM (by design)
2
VI1  VI2 V
VICM VOCM.2 # OCM IRU5M   5G 
2 1 A v
Figure 29. Single-Ended In to Differential Out

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Typical Applications (continued)

9.2.3 Single Supply Operation
The input stage of the LMH6551 has a built in offset of 0.7 V towards the lower supply to accommodate single
supply operation with single-ended inputs. As shown in Figure 29, the input common-mode voltage is less than
the output common voltage. It is set by current flowing through the feedback network from the device output. The
input common-mode range of 0.4 V to 3.2 V places constraints on gain settings. Possible solutions to this
limitation include AC coupling the input signal, using split power supplies and limiting stage gain. AC coupling
with single supply is shown in Figure 30.
In Figure 29 closed loop gain = VO / VI ≊ RF / RG, where VI =VS / 2, as long as RM << RG. Note that in single-
ended to differential operation VI is measured single-ended while VO is measured differentially. This means that
gain is really 1/2 or 6 dB less when measured on either of the output pins separately. Additionally, note that the
input signal at RT (labeled as VI) is 1/2 of VS when RT is chosen to match RS to RIN.
VICM = Input common-mode voltage = (VI1+VI2) / 2.

RF
RO

VO1
RG VI1
RS
+
CL RL VO
VCM
VI a RT
-
RG
VI2
RM VO2

RO
RF

VO1 + VO2 VICM = VOCM

*VCM = VI1 + VI2
2
VICM =
*BY DESIGN 2

Figure 30. AC-Coupled for Single Supply Operation

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Typical Applications (continued)

9.2.4 Driving Analog-to-Digital Converters
Analog-to-digital converters (ADC) present challenging load conditions. They typically have high-impedance
inputs with large and often variable capacitive components. As well, there are usually current spikes associated
with switched capacitor or sample and hold circuits. Figure 31 shows a typical circuit for driving an ADC. The two
56-Ω resistors serve to isolate the capacitive loading of the ADC from the amplifier and ensure stability. In
addition, the resistors form part of a low pass filter which helps to provide anti alias and noise reduction
functions. The two 39-pF capacitors help to smooth the current spikes associated with the internal switching
circuits of the ADC and also are a key component in the low pass filtering of the ADC input. In the circuit of
Figure 31the cutoff frequency of the filter is 1/ (2*π*56 Ω *(39 pF + 14pF)) = 53 MHz (which is slightly less than
the sampling frequency). Note that the ADC input capacitance must be factored into the frequency response of
the input filter, and that being a differential input the effective input capacitance is double. Also as shown in
Figure 31 the input capacitance to many ADCs is variable based on the clock cycle. See the data sheet for your
particular ADC for details.

RF1
56
ADC12LO66

RG1 39 pF
+
VI a VCM
- 7 - 8 pF
39 pF
RG2

56
VREF
RF2

1V LOW IMPEDANCE
VOLTAGE REFERENCE

Figure 31. Driving an ADC

The amplifier and ADC should be located as closely together as possible. Both devices require that the filter
components be in close proximity to them. The amplifier needs to have minimal parasitic loading on the output
traces and the ADC is sensitive to high frequency noise that may couple in on its input lines. Some high
performance ADCs have an input stage that has a bandwidth of several times its sample rate. The sampling
process results in all input signals presented to the input stage mixing down into the Nyquist range (DC to Fs/2).
See AN-236 for more details on the subsampling process and the requirements this imposes on the filtering
necessary in your system.

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Typical Applications (continued)

9.2.5 Using Transformers
Transformers are useful for impedance transformation as well as for single to differential, and differential to
single-ended conversion. A transformer can be used to step up the output voltage of the amplifier to drive very
high impedance loads as shown in Figure 32. Figure 34 shows the opposite case where the output voltage is
stepped down to drive a low-impedance load.
Transformers have limitations that must be considered before choosing to use one. Compared to a differential
amplifier, the most serious limitations of a transformer are the inability to pass DC and balance error (which
causes distortion and gain errors). For most applications the LMH6551 will have adequate output swing and drive
current and a transformer will not be desirable. Transformers are used primarily to interface differential circuits to
50-Ω single-ended test equipment to simplify diagnostic testing.

300: TWISTED PAIR

500
37.5: 1:2 (TURNS)

250
+
4 VPP a VCM
VCM
-
250
8 VPP
RL = 300:
37.5:
500

AV = 2

Figure 32. Transformer Out High-Impedance Load

VIN * AV * N
VL = ©
§ 2 ROUT * N2 ¨
¨ +1 ¨
¨ RL
§
©
WHERE VIN = DIFFERENTIAL INPUT VOLTAGE
§ SECONDARY
©
¨
¨
N = TRANSFORMER TURNS RATIO = ¨ PRIMARY
¨
©
§

AV = CLOSED LOOP AMPLIFIER GAIN

ROUT = SERIES OUTPUT MATCHING RESISTOR
RL = LOAD RESISTOR
VL = VOLTAGE ACROSS LOAD RESISTOR

Figure 33. Calculating Transformer Circuit Net Gain

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Typical Applications (continued)

100: TWISTED PAIR

375
200: 2:1 (TURNS)

375
+
4 VPP a VCM
VCM
-
375
1 VPP
RL = 100:
200:
375
AV = 1

Figure 34. Transformer Out Low-Impedance Load

50: COAX

375
100: 2:1 (TURNS)

375
+
4 VPP a VCM
C1
-
375
1 VPP
100:
375

GAIN = 1
C1 IS NOT REQUIRED IF VCM = GROUND

Figure 35. Driving 50-Ω Test Equipment

10 Power Supply Recommendations

The LMH6551 can be used with any combination of positive and negative power supplies as long as the
combined supply voltage is between 4.5 V and 12 V. The LMH6551 will provide best performance when the
output voltage is set at the mid supply voltage, and when the total supply voltage is between 9 V and 12 V.
When selecting a supply voltage that is less than 9 V, it is important to consider both the input common-mode
voltage range as well as the output voltage range.
Power supply bypassing as shown in Figure 25 and Figure 26 is important and power supply regulation should
be within 5% or better when using a supply voltage near the edges of the operating range.

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11 Layout

11.1 Layout Guidelines

The LMH6551 is a very high performance amplifier. In order to get maximum benefit from the differential circuit
architecture, board layout and component selection is very critical. The circuit board should have a low
inductance ground plane and well bypassed broad supply lines. External components should be leadless surface
mount types. The feedback network and output matching resistors should be composed of short traces and
precision resistors (0.1%). The output matching resistors should be placed within 3-4 mm of the amplifier as
should the supply bypass capacitors. The LMH730154 evaluation board is an example of good layout
techniques.
The LMH6551 is sensitive to parasitic capacitances on the amplifier inputs and to a lesser extent on the outputs
as well. Ground and power plane metal should be removed from beneath the amplifier and from beneath RF and
RG.
With any differential signal path symmetry is very important. Even small amounts of asymmetry will contribute to
distortion and balance errors.
Texas Instruments offers evaluation board(s) to aid in device testing and characterization and as a guide for
proper layout. Generally, a good high frequency layout will keep power supply and ground traces away from the
inverting input and output pins. Parasitic capacitances on these nodes to ground will cause frequency response
peaking and possible circuit oscillations.

11.2 Layout Example

Figure 36. Layout Schematic

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11.3 Power Dissipation

The LMH6551 is optimized for maximum speed and performance in the small form factor of the standard SOIC
package, and is essentially a dual channel amplifier. To ensure maximum output drive and highest performance,
thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAXof 150°C is
never exceeded due to the overall power dissipation.
Follow these steps to determine the Maximum power dissipation for the LMH6551:
1. Calculate the quiescent (no-load) power:
PAMP = ICC* (VS)
where
• VS = V+ - V− (1)
Be sure to include any current through the feedback network if VOCM is not mid rail.
2. Calculate the RMS power dissipated in each of the output stages:
PD (rms) = rms ((VS - V+OUT) * I+OUT) + rms ((VS − V−OUT) * I−OUT)
where
• VOUT and IOUT are the voltage and the current measured at the output pins of the differential amplifier as if they
were single-ended amplifiers and VS is the total supply voltage (2)
3. Calculate the total RMS power:
PT = PAMP + PD. (3)
The maximum power that the LMH6551 package can dissipate at a given temperature can be derived with the
following equation:
PMAX = (150° – TAMB)/ θJA
where
• TAMB = Ambient temperature (°C)
• θJA = Thermal resistance, from junction to ambient, for a given package (°C/W)
• For the SOIC package θJA is 150°C/W. (4)

NOTE
If VCM is not 0 V then there will be quiescent current flowing in the feedback network. This
current should be included in the thermal calculations and added into the quiescent power
dissipation of the amplifier.

11.4 ESD Protection

The LMH6551 is protected against electrostatic discharge (ESD) on all pins. The LMH6551 will survive 2000 V
Human Body model and 200 V Machine model events. Under normal operation the ESD diodes have no effect
on circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6551 is
driven by a large signal while the device is powered down the ESD diodes will conduct. The current that flows
through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is
possible to power up a chip with a large signal applied to the input pins.

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12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation, see the following:
• OA-15 Frequent Faux Pas in Applying Wideband Current Feedback Amplifiers, SNOA367
• AN-236 An Introduction to the Sampling Theorem, SNAA079

12.2 Trademarks
LMH is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

LMH6551MA/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH65 Samples
51MA
LMH6551MAX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 LMH65 Samples
51MA
LMH6551MM/NOPB ACTIVE VSSOP DGK 8 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 AU1A Samples

LMH6551MMX/NOPB ACTIVE VSSOP DGK 8 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 AU1A Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 17-Oct-2024

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Oct-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LMH6551MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6551MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMH6551MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Oct-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6551MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6551MM/NOPB VSSOP DGK 8 1000 208.0 191.0 35.0
LMH6551MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-Oct-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
LMH6551MA/NOPB D SOIC 8 95 495 8 4064 3.05

Pack Materials-Page 3
 PACKAGE OUTLINE
DGK0008A SCALE 4.000
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
TYP
A 4.75
0.1 C
PIN 1 INDEX AREA
SEATING
PLANE
6X 0.65
8
1

2X
3.1
1.95
2.9
NOTE 3

4
5 0.38
8X
0.25
3.1 0.13 C A B
B
2.9
NOTE 4

0.23
0.13

SEE DETAIL A
0.25
GAGE PLANE

1.1 MAX

0.7 0.15
0 -8 0.4 0.05
DETAIL A
A 20

TYPICAL

4214862/A 04/2023
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187.

www.ti.com
 EXAMPLE BOARD LAYOUT
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

SYMM
8X (1.4) (R0.05) TYP

8X (0.45) 1 8

SYMM

6X (0.65)
5
4

SEE DETAILS

(4.4)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 15X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214862/A 04/2023
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
9. Size of metal pad may vary due to creepage requirement.

www.ti.com
 EXAMPLE STENCIL DESIGN
TM
DGK0008A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

SYMM

8X (1.4) (R0.05) TYP

8X (0.45) 1 8

SYMM

6X (0.65)
5
4

(4.4)

SOLDER PASTE EXAMPLE

SCALE: 15X

4214862/A 04/2023
NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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