3-1/2 DIGIT

ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126
TC7126A
TC7126A

3-1/2 DIGIT ANALOG-TO-DIGITAL CONVERTERS

FEATURES GENERAL DESCRIPTION

■ Low Temperature Drift Internal Reference The TC7126A is a 3-1/2 digit CMOS analog-to-digital
TC7126 ...................................... 80 ppm/°C Typ. converter (ADC) containing all the active components nec-
TC7126A .................................... 35 ppm/°C Typ. essary to construct a 0.05% resolution measurement sys-
■ Guaranteed Zero Reading With Zero Input tem. Seven-segment decoders, digit and polarity drivers,
■ Low Noise ..................................................... 15µVP-P voltage reference, and clock circuit are integrated on-chip.
■ High Resolution .............................................. 0.05% The TC7126A directly drives a liquid crystal display (LCD),
■ Low Input Leakage Current ...................... 1pA Typ. and includes a backplane driver.
10pA Max A low-cost, high-resolution indicating meter requires
■ Precision Null Detectors With True Polarity at only a display, four resistors, and four capacitors. The
Zero TC7126A's extremely low power drain and 9V battery
■ High-Impedance Differential Input operation make it ideal for portable applications.
■ Convenient 9V Battery Operation With The TC7126A reduces linearity error to less than 1
Low Power Dissipation ........................ 500µW Typ. count. Roll-over error (the difference in readings for equal
900µW Max magnitude but opposite polarity input signals) is below ±1
count. High-impedance differential inputs offer 1 pA leak-
TYPICAL APPLICATIONS age current and a 1012Ω input impedance. The 15 µVP-P
noise performance guarantees a "rock solid" reading, and
■ Thermometry
the auto-zero cycle guarantees a zero display reading with
■ Bridge Readouts: Strain Gauges, Load Cells, Null
a 0V input.
Detectors
The TC7126A features a precision, low-drift internal
■ Digital Meters and Panel Meters
voltage reference and is functionally identical to the TC7126.
— Voltage/Current/Ohms/Power, pH
A low-drift external reference is not normally required with
■ Digital Scales, Process Monitors
the TC7126A.

TYPICAL OPERATING CIRCUIT ORDERING INFORMATION

PART CODE TC7126X X XXX
0.1 µF A or blank*
34 33
C+ C–
LCD R (reversed pins) or blank (CPL pkg only)
1 MΩ REF REF
31 2–19 SEGMENT
+ V+
IN * "A" parts have an improved reference TC
22–25 DRIVE
ANALOG 0.01 µF
INPUT – 20
30 V IN POL
– MINUS SIGN Package Code (see below):
21 BACKPLANE
BP
32 ANALOG
COMMON 1
V
+
Package Temperature
28
VBUFF 240 kΩ +
Code Package Range
TC7126
0.33 TC7126A 9V
180 kΩ
µF + 36 CKW 44-Pin PQFP 0°C to +70°C
29 VREF
CAZ 10 kΩ
–
CLW 44-Pin PLCC 0°C to +70°C
0.15 µF V REF 35
27
VINT V–
26 CPL 40-Pin PDIP 0°C to +70°C
OSC2 OSC3 OSC1 1 CONVERSION/SEC
IPL 40-Pin PDIP (non-A only) – 25°C to +85°C
39 38 COSC 40
TO ANALOG COMMON
ROSC 50 pF (PIN 32) AVAILABLE PACKAGES
560 kΩ NOTE: Pin numbers refer to 40-pin DIP.

40-Pin Plastic DIP 44-Pin Plastic Quad Flat 44-Pin Plastic Chip
Package Formed Leads Carrier PLCC

TC7126/A-8 11/6/96 TelCom Semiconductor reserves the right to make changes in the circuitry and specifications of its devices.
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 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
ABSOLUTE MAXIMUM RATINGS*
Supply Voltage (V+ to V–)......................................... +15V Power Dissipation (TA ≤ 70°C) (Note 2)
Analog Input Voltage (Either Input) (Note 1) ........ V+ to V – 44-Pin PQFP .................................................... 1.00W
Reference Input Voltage (Either Input) ................. V+ to V – 44-Pin PLCC .....................................................1.23W
Clock Input ...................................................... TEST to V+ 40-Pin PDIP ......................................................1.23W
Operating Temperature Range *Static-sensitive device. Unused devices must be stored in conductive
C Devices .............................................. 0°C to +70°C material. Protect devices from static discharge and static fields. Stresses
I Devices ........................................... – 25°C to +85°C above those listed under Absolute Maximum Ratings may cause perma-
Storage Temperature Range ................ – 65°C to +150°C nent damage to the device. These are stress ratings only and functional
Lead Temperature (Soldering, 10 sec) ................. +300°C operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied.
Exposure to Absolute Maximum Rating Conditions for extended periods
may affect device reliability.

ELECTRICAL CHARACTERISTICS: VS = +9V, fCLK = 16kHz, and TA = +25°C, unless otherwise noted.
Symbol Parameter Test Conditions Min Typ Max Unit
Input
Zero Input Reading VIN = 0V –000.0 ±000.0 +000.0 Digital
Full Scale = 200mV Reading
Zero Reading Drift VIN = 0V, 0°C ≤ TA ≤ +70°C — 0.2 1 µV/°C
Ratiometric Reading VIN = VREF, VREF = 100mV 999 999/1000 1000 Digital
Reading
NL Linearity Error Full Scale = 200mV or 2V –1 ±0.2 1 Count
Max Deviation From Best Fit
Straight Line
Roll-Over Error –VIN = +VIN ≈ 200mV –1 ±0.2 1 Count
eN Noise VIN = 0V, Full Scale = 200mV — 15 — µVP-P
IL Input Leakage Current VIN = 0V — 1 10 pA
CMRR Common-Mode Rejection VCM = ±1V, VIN = 0V, — 50 — µV/V
Ratio Full Scale = 200mV
Scale Factor Temperature VIN = 199mV, 0°C ≤ TA ≤ +70°C — 1 5 ppm/°C
Coefficient Ext Ref Temp Coeff = 0ppm/°C
Analog Common
VCTC Analog Common 250kΩ Between Common and V + — — — —
Temperature Coefficient 0°C ≤ TA ≤ +70°C ("C" Devices): — — — —
TC7126 — 80 — ppm/°C
TC7126A — 35 75 ppm/°C
– 25°C ≤ TA ≤ +85°C ("I" Device):
TC7126A — 35 100 ppm/°C
VC Analog Common Voltage 250kΩ Between Common and V+ 2.7 3.05 3.35 V
LCD Drive
VSD LCD Segment Drive Voltage V + to V – = 9V 4 5 6 VP-P
VBD LCD Backplane Drive Voltage V+ to V– = 9V 4 5 6 VP-P
Power Supply
IS Power Supply Current VIN = 0V, V + to V – = 9V (Note 6) — 55 100 µA
NOTES: 1. Input voltage may exceed supply voltages when input current is limited to 100µA.
2. Dissipation rating assumes device is mounted with all leads soldered to PC board.
3. Refer to "Differential Input" discussion.
4. Backplane drive is in-phase with segment drive for "OFF" segment and 180° out-of-phase for "ON" segment. Frequency is 20 times
conversion rate. Average DC component is less than 50mV.
5. See "Typical Operating Circuit."
6. During auto-zero phase, current is 10–20 µA higher. A 48kHz oscillator increases current by 8µA (typical). Common current not
included.
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3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
PIN CONFIGURATIONS

COMMON

VBUFF
OSC 1
OSC 2
OSC 3

C REF
C–REF
VREF
VREF

VREF
TEST

VINT
CAZ
VIN

VIN
+ +
NC
V+

V–
A1

B1
C1
D1

–
6 5 4 3 2 1 44 43 42 41 40 44 43 42 41 40 39 38 37 36 35 34

– NC 1 33 NC
F1 7 39 VREF
G1 8 + NC 2 32 G
38 C REF 2
E1 9 – TEST 3 31 C 3
37 C REF

D2 10 36 COMMON OSC 3 4 30 A 3
+ NC 5 29 G 3
C2 11 35 VIN

34 NC OSC 2 6 28 BP
NC 12 TC7126CLW TC7126CKW
B2 13 TC7126ACLW – OSC 1 7 TC7126ACKW 27 POL
33 VIN
(PLCC) (FLAT PACKAGE)
A 2 14 32 CAZ V+ 8 26 AB 4

F 2 15 31 VBUFF D1 9 25 E3

E 2 16 30 VINT C 1 10 24 F3

D 3 17 29 V – B 1 11 23 B3

18 19 20 21 22 23 24 25 26 27 28 12 13 14 15 16 17 18 19 20 21 22
AB4
B3
F3
E3

G3
A3

C3

G2
POL

BP

D3
NC

A1
F1
G1
E1

D2
C2
B2
A2
F2

E2
V+ 1 40 OSC 1 OSC1 1 40 V +
NORMAL PIN REVERSE PIN
D1 2 CONFIGURATION 39 OSC2 OSC2 2 CONFIGURATION 39 D1
C1 3 38 OSC 3 OSC 3 3 38 C1
B1 4 37 TEST TEST 4 37 B1
+ +
1's A1 5 36 V REF V REF 5 36 A1 1's
–
F1 6 35 V – VREF 6 35 F1
REF
+ +
G1 7 34 CREF CREF 7 34 G1
– –
E1 8 33 CREF CREF 8 33 E 1
ANALOG 9
D2 9 32 ANALOG COMMON
32 D2
COMMON
+ +
C2 10 31 V IN V IN 10 31 C2
TC7126CPL TC7126RCPL
B2 11 30 V –
IN V– IN 11 30 B2
TC7126ACPL TC7126ARCPL 10's
10's
A2 12 TC7126IPL 29 CAZ CAZ 12 TC7126RIPL 29 A2
TC7126AIPL TC7126ARIPL
F2 13 28 VBUFF VBUFF 13 28 F2
E 2 14 27 V INT V INT 14 27 E 2
D3 15 26 V – V – 15 26 D3
B3 16 25 G G 2 16 25 B3
2
100's 100's
F3 17 24 C 3 C 3 17 24 F3
100's 100's
E 3 18 23 A 3 A 3 18 23 E 3
1000's AB4 19 22 G 3 G 3 19 22 AB4 1000's
POL 20 21 BP BP 20 21 POL
(MINUS SIGN) (BACKPLANE) (BACKPLANE) (MINUS SIGN)

NC = NO INTERNAL CONNECTION

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 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
PIN DESCRIPTION
Pin No.
40-Pin PDIP
Normal (Reverse) Name Description
1 (40) V+ Positive supply voltage.
2 (39) D1 Activates the D section of the units display.
3 (38) C1 Activates the C section of the units display.
4 (37) B1 Activates the B section of the units display.
5 (36) A1 Activates the A section of the units display.
6 (35) F1 Activates the F section of the units display.
7 (34) G1 Activates the G section of the units display.
8 (33) E1 Activates the E section of the units display.
9 (32) D2 Activates the D section of the tens display.
10 (31) C2 Activates the C section of the tens display.
11 (30) B2 Activates the B section of the tens display.
12 (29) A2 Activates the A section of the tens display.
13 (28) F2 Activates the F section of the tens display.
14 (27) E2 Activates the E section of the tens display.
15 (26) D3 Activates the D section of the hundreds display.
16 (25) B3 Activates the B section of the hundreds display.
17 (24) F3 Activates the F section of the hundreds display.
18 (23) E3 Activates the E section of the hundreds display.
19 (22) AB4 Activates both halves of the 1 in the thousands display.
20 (21) POL Activates the negative polarity display.
21 (20) BP Backplane drive output.
22 (19) G3 Activates the G section of the hundreds display.
23 (18) A3 Activates the A section of the hundreds display.
24 (17) C3 Activates the C section of the hundreds display.
25 (16) G2 Activates the G section of the tens display.
26 (15) V– Negative power supply voltage.
27 (14) VINT The integrating capacitor should be selected to give the maximum voltage swing
that ensures component tolerance buildup will not allow the integrator output to
saturate. When analog common is used as a reference and the conversion rate is
3 readings per second, a 0.047 µF capacitor may be used. The capacitor must
have a low dielectric constant to prevent roll-over errors. See "Integrating Capaci-
tor" section for additional details.
28 (13) VBUFF Integration resistor connection. Use a 180 kΩ resistor for a 200 mV full-scale
range and a 1.8 MΩ resistor for a 2V full-scale range.
29 (12) CAZ The size of the auto-zero capacitor influences system noise. Use a 0.33 µF
capacitor for 200 mV full scale, and a 0.033 µF capacitor for 2V full scale. See
paragraph on auto-zero capacitor for more details.
30 (11) VIN– The low input signal is connected to this pin.
31 (10) VIN+ The high input signal is connected to this pin.
32 (9) ANALOG This pin is primarily used to set the analog common-mode voltage for battery
COMMON operation or in systems where the input signal is referenced to the power supply.
See paragraph on analog common for more details. It also acts as a reference
voltage source.
33 (8) C-REF See pin 34.

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3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
PIN DESCRIPTION (Cont.)
Pin No.
40-Pin PDIP
Normal (Reverse) Name Description
+
34 (7) CREF A 0.1µF capacitor is used in most applications. If a large common-mode voltage
–
exists (for example, the VIN pin is not at analog common), and a 200mV scale is
used, a 1µF capacitor is recommended and will hold the roll-over error to 0.5
count.
–
35 (6) VREF See pin 36.
+
(5) VREF The analog input required to generate a full-scale output (1999 counts). Place 100
mV between pins 35 and 36 for 199.9 mV full scale. Place 1V between pins 35
and 36 for 2V full scale. See paragraph on reference voltage.
36 (4) TEST Lamp test. When pulled HIGH (to V+), all segments will be turned ON and the
display should read –1888. It may also be used as a negative supply for exter-
nally-generated decimal points. See paragraph under test for additional informa-
tion.
37 (3) OSC3 See pin 40.
38 (2) OSC2 See pin 40.
40 (1) OSC1 Pins 40, 39 and 38 make up the oscillator section. For a 48kHz clock (3 readings
39 per second), connect pin 40 to the junction of a 180kΩ resistor and a 50pF
capacitor. The 180kΩ resistor is tied to pin 39 and the 50 pF capacitor is tied to
pin 38.

GENERAL THEORY OF OPERATION

ANALOG
(All Pin Designations Refer to the 40-Pin DIP) INPUT
INTEGRATOR
SIGNAL
– COMPARATOR
–
Dual-Slope Conversion Principles
+
+
The TC7126A is a dual-slope, integrating analog-to-
digital converter. An understanding of the dual-slope con-
version technique will aid in following detailed TC7126A SWITCH
operational theory. DRIVER
CLOCK
The conventional dual-slope converter measurement REF PHASE CONTROL
VOLTAGE CONTROL LOGIC
cycle has two distinct phases: POLARITY CONTROL
(1) Input signal integration
(2) Reference voltage integration (deintegration)
COUNTER
DISPLAY
INTEGRATOR

The input signal being converted is integrated for a

OUTPUT

fixed time period (tSI), measured by counting clock pulses. VIN ' VFULL SCALE
An opposite polarity constant reference voltage is then VIN ' 1.2 VFULL SCALE
integrated until the integrator output voltage returns to
zero. The reference integration time is directly proportional FIXED VARIABLE
to the input signal (tRI). SIGNAL REFERENCE
INTEGRATE INTEGRATE
In a simple dual-slope converter, a complete conver- TIME TIME
sion requires the integrator output to "ramp-up" and "ramp-
down."
A simple mathematical equation relates the input signal, Figure 1. Basic Dual-Slope Converter
reference voltage, and integration time:
where:

∫0
tSI VR = Reference voltage
1 VR tRI
VIN(t) dt = , tSI = Signal integration time (fixed)
RC RC
tRI = Reference voltage integration time (variable).
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 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
analog gates close a feedback loop around the integrator
30 and comparator. This loop permits comparator offset volt-
age error compensation. The voltage level established on
NORMAL MODE REJECTION (dB)

CAZ compensates for device offset voltages. The auto-zero

phase residual is typically 10 µV to 15 µV.
20 The auto-zero cycle length is 1000 to 3000 clock
periods.

Signal Integration Phase

10
The auto-zero loop is entered and the internal differen-
+ –
tial inputs connect to VIN and VIN . The differential input signal
t = MEASUREMENT PERIOD is integrated for a fixed time period. The TC7126A signal
integration period is 1000 clock periods, or counts. The
0
0.1/t 1/t 10/t externally-set clock frequency is 44 before clocking the
INPUT FREQUENCY internal counters. The integration time period is:
Figure 2. Normal-Mode Rejection of Dual-Slope Converter 4
tSI = 3 1000,
fOSC
For a constant VIN: where fOSC = external clock frequency.

VIN = VR ( tt ).
RI
SI
The differential input voltage must be within the device
common-mode range when the converter and measured
The dual-slope converter accuracy is unrelated to the system share the same power supply common (ground). If
integrating resistor and capacitor values, as long as they are the converter and measured system do not share the same
stable during a measurement cycle. Noise immunity is an power supply common, VIN –
should be tied to analog com-
inherent benefit. Noise spikes are integrated, or averaged, mon.
to zero during integration periods. Integrating ADCs are Polarity is determined at the end of signal integrate
immune to the large conversion errors that plague succes- phase. The sign bit is a true polarity indication, in that signals
sive approximation converters in high-noise environments. less than 1 LSB are correctly determined. This allows
Interfering signals with frequency components at multiples precision null detection limited only by device noise and
of the averaging period will be attenuated. Integrating ADCs auto-zero residual offsets.
commonly operate with the signal integration period set to a
multiple of the 50Hz/60Hz power line period. Reference Integrate Phase
ANALOG SECTION The third phase is reference integrate, or deintegrate.
– +
VIN is internally connected to analog common and VIN is
In addition to the basic integrate and deintegrate dual- connected across the previously-charged reference capaci-
slope cycles discussed above, the TC7126A design incor- tor. Circuitry within the chip ensures that the capacitor will be
porates an auto-zero cycle. This cycle removes buffer connected with the correct polarity to cause the integrator
amplifier, integrator, and comparator offset voltage error output to return to zero. The time required for the output to
terms from the conversion. A true digital zero reading results return to zero is proportional to the input signal and is
without external adjusting potentiometers. A complete con- between 0 and 2000 internal clock periods. The digital
version consists of three phases: reading displayed is:
(1) Auto-zero phase
VIN
(2) Signal integrate phase 1000
VREF
(3) Reference integrate phase
DIGITAL SECTION
Auto-Zero Phase
The TC7126A contains all the segment drivers neces-
During the auto-zero phase, the differential input signal sary to directly drive a 3-1/2 digit LCD. An LCD backplane
is disconnected from the circuit by opening internal analog driver is included. The backplane frequency is the external
gates. The internal nodes are shorted to analog common clock frequency 4 800. For 3 conversions per second the
(ground) to establish a zero input condition. Additional backplane frequency is 60Hz with a 5V nominal amplitude.
6
 TYPICAL SEGMENT OUTPUT
3-1/2 DIGIT

+
V

0.5 mA
SEGMENT
OUTPUT
LCD
2 mA

TC7126A INTERNAL DIGITAL GROUND

BP
21

CAZ CINT
CREF RINT
+ + – – + LCD SEGMENT DRIVERS
C REF VREF VREF C REF V BUFF V VINT

34 36 35 33 28 1 29 27
INTEGRATOR 7 SEGMENT 7 SEGMENT 7 SEGMENT
TO DECODE
4200
DECODE DECODE
– – DIGITAL
ANALOG-TO-DIGITAL CONVERTERS

ZI & + SECTION
10 ZI & AZ
AZ + +
µA DATA LATCH
–

7
ZI AZ
+ 31
V IN COMPARATOR
DE DE THOUSANDS HUNDREDS TENS UNITS
INT (–) (+)

LOW
– TEMPCO TO SWITCH DRIVERS
VREF FROM COMPARATOR OUTPUT 1
+ +
V

Figure 3. TC7126A Block Diagram

32 DE (+) DE (–)
ANALOG
COMMON V+– 2.8V CLOCK fOSC
÷4 CONTROL LOGIC 6.2V
– AZ & DE (±)
V IN
INT 26 TEST
INTERNAL DIGITAL GOUND 500Ω
– VTH
V
= 1V
26
V–
40 39 38
OSC 1 OSC 2 OSC 3

ROSC
COSC
TC7126
TC7126A
 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
When a segment driver is in-phase with the backplane The TC7126A is a drop-in replacement for the TC7126
signal, the segment is OFF. An out-of-phase segment drive and ICL7126 that offers a greatly improved internal refer-
signal causes the segment to be ON, or visible. This AC drive ence temperature coefficient. No external component value
configuration results in negligible DC voltage across each changes are required to upgrade existing designs.
LCD segment, ensuring long LCD life. The polarity segment
+ –
driver is ON for negative analog inputs. If VIN and VIN are COMPONENT VALUE SELECTION
reversed, this indicator would reverse.
Auto-Zero Capacitor (CAZ)
On the TC7126A, when the TEST pin is pulled to V+, all
segments are turned ON. The display reads –1888. During The CAZ size has some influence on system noise. A
this mode, LCD segments have a constant DC voltage 0.33µF capacitor is recommended for 200mV full-scale
impressed. DO NOT LEAVE THE DISPLAY IN THIS MODE applications where 1 LSB is 100µV. A 0.033µF capacitor is
FOR MORE THAN SEVERAL MINUTES; LCDS MAY BE adequate for 2V full-scale applications. A Mylar-type dielec-
DESTROYED IF OPERATED WITH DC LEVELS FOR tric capacitor is adequate.
EXTENDED PERIODS.
The display font and segment drive assignment are Reference Voltage Capacitor (CREF)
shown in Figure 4.
The reference voltage, used to ramp the integrator
output voltage back to zero during the reference integrate
System Timing phase, is stored on CREF. A 0.1µF capacitor is acceptable
–
The oscillator frequency is 44 prior to clocking the when VREF is tied to analog common. If a large common-
–
internal decade counters. The three-phase measurement mode voltage exists (VREF ≠ analog common) and the
cycle takes a total of 4000 counts (16,000 clock pulses). application requires a 200 mV full scale, increase CREF to
The 4000-count cycle is independent of input signal magni- 1 µF. Roll-over error will be held to less than 0.5 count. A
tude. Mylar-type dielectric capacitor is adequate.
Each phase of the measurement cycle has the following
length: Integrating Capacitor (CINT)
(1) Auto-zero phase: 1000 to 3000 counts CINT should be selected to maximize integrator output
(4000 to 12,000 clock pulses) voltage swing without causing output saturation. Due to
For signals less than full scale, the auto-zero phase the TC7126A's superior analog common temperature co-
is assigned the unused reference integrate time efficient specification, analog common will normally sup-
period. ply the differential voltage reference. For this case, a ±2V
(2) Signal integrate: 1000 counts full-scale integrator output swing is satisfactory. For 3
(4000 clock pulses) readings per second (fOSC = 48 kHz), a 0.047µF value is
suggested. For 1 reading per second, 0.15 µF is recom-
This time period is fixed. The integration period is:
mended. If a different oscillator frequency is used, CINT
1 must be changed in inverse proportion to maintain the
tSI = 4000 ,
fOSC nominal ±2V integrator swing.
An exact expression for CINT is:
where fOSC is the externally-set clock frequency.
(3) Reference integrate: 0 to 2000 counts
(0 to 8000 clock pulses)
CINT =
(4000) ( )( )
1
fOSC
VFS
RINT
,
DISPLAY FONT VINT
where: fOSC = Clock frequency at pin 38
VFS = Full-scale input voltage
RINT = Integrating resistor
1000's 100's 10's 1's VINT = Desired full-scale integrator output swing.

At 3 readings per second, a 750Ω resistor should be

placed in series with CINT. This increases accuracy by
compensating for comparator delay. CINT must have low
dielectric absorption to minimize roll-over error. A polypro-
Figure 4. Display Font and Segment Assignment pylene capacitor is recommended.
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3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
Integrating Resistor (RINT) input voltage by two, the reference voltage should be set to
200mV. This permits the transducer input to be used di-
The input buffer amplifier and integrator are designed rectly.
with Class A output stages. The output stage idling current The differential reference can also be used where a
is 6µA. The integrator and buffer can supply 1µA drive digital zero reading is required when VIN is not equal to zero.
current with negligible linearity errors. RINT is chosen to This is common in temperature-measuring instrumentation.
remain in the output stage linear drive region, but not so A compensating offset voltage can be applied between
large that PC board leakage currents induce errors. For a analog common and VIN –
. The transducer output is con-
200mV full scale, RINT is 180kΩ. A 2V full scale requires +
nected between VIN and analog common.
1.8MΩ.

Component Nominal Full-Scale Voltage

DEVICE PIN FUNCTIONAL DESCRIPTION
(Pin Numbers Refer to 40-Pin DIP)
Value 200 mV 2V
Differential Signal Inputs
CAZ 0.33 µF 0.033 µF + –
VIN (Pin 31), VIN (Pin 30)
RINT 180 kΩ 1.8 MΩ
The TC7126A is designed with true differential inputs
CINT 0.047 µF 0.047 µF
and accepts input signals within the input stage common-
NOTE: fOSC = 48kHz (3 readings per sec).
mode voltage range (VCM). Typical range is V+ – 1V to
V–+1V. Common-mode voltages are removed from the
Oscillator Components system when the TC7126A operates from a battery or
COSC should be 50pF; ROSC is selected from the equa- floating power source (isolated from measured system), and
–
tion: VIN is connected to analog common (VCOM). (See Figure 5.)
In systems where common-mode voltages exist, the
0.45 TC7126A's 86 dB common-mode rejection ratio minimizes
fOSC = .
RC error. Common-mode voltages do, however, affect the inte-
For a 48 kHz clock (3 conversions per second), R = 180kΩ. grator output level. A worst-case condition exists if a large
positive VCM exists in conjunction with a full-scale negative
Note that fOSC is 44 to generate the TC7126A's inter- differential signal. The negative signal drives the integrator
nal clock. The backplane drive signal is derived by dividing output positive along with VCM (see Figure 6.) For such
fOSC by 800. applications, the integrator output swing can be reduced
To achieve maximum rejection of 60Hz noise pickup, below the recommended 2V full-scale swing. The integrator
the signal integrate period should be a multiple of 60Hz. output will swing within 0.3V of V+ or V– without increased
Oscillator frequencies of 24kHz, 12kHz, 80kHz, 60kHz, linearity error.
40kHz, etc. should be selected. For 50Hz rejection, oscilla-
tor frequencies of 20kHz, 100kHz, 66-2/3kHz, 50kHz, 40kHz, Differential Reference
+ –
etc. would be suitable. Note that 40kHz (2.5 readings per VREF (Pin 36), VREF (Pin 35)
second) will reject both 50Hz and 60Hz. The reference voltage can be generated anywhere
within the V+ to V– power supply range.
Reference Voltage Selection To prevent roll-over type errors being induced by large
common-mode voltages, CREF should be large compared to
A full-scale reading (2000 counts) requires the input
stray node capacitance.
signal be twice the reference voltage.
The TC7126A offers a significantly improved analog
common temperature coefficient. This potential provides a
very stable voltage, suitable for use as a voltage reference.
Required Full-Scale Voltage* VREF The temperature coefficient of analog common is typically
20 mV 100mV 35 ppm/°C for the TC7126A and 80 ppm/°C for the TC7126.
2V 1V
ANALOG COMMON (Pin 32)
*VFS = 2 VREF.
The analog common pin is set at a voltage potential
In some applications, a scale factor other than unity may approximately 3V below V+. The potential is guaranteed to
exist between a transducer output voltage and the required be between 2.7V and 3.35V below V+. Analog common is
digital reading. Assume, for example, a pressure transducer tied internally to an N-channel FET capable of sinking
output for 2000lb/in.2 is 400mV. Rather than dividing the 100µA. This FET will hold the common line at 3V should an
9
 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A

SEGMENT
DRIVE LCD

MEASURED VBUFF CAZ VINT POL BP

SYSTEM + OSC1
VIN
+
V – OSC3
VIN TC7126A
V– GND ANALOG – OSC2
+ +
COMMON VREF VREF V V–
V+ V – GND
POWER +
SOURCE 9V

Figure 5. Common-Mode Voltage Removed in Battery Operation With VIN = Analog Common

external load attempt to pull the common line toward V+. respect to the TC7126A's power source. The analog com-
Analog common source current is limited to 1µA. Therefore, mon potential of V+ – 3V gives a 7V end of battery life
analog common is easily pulled to a more negative voltage voltage. The common potential has a 0.001%/% voltage
(i.e., below V+ – 3V). coefficient and a 15Ω output impedance.
+ –
The TC7126A connects the internal VIN and VIN With sufficiently high total supply voltage (V+ – V– >7V),
inputs to analog common during the auto-zero phase. analog common is a very stable potential with excellent
–
During the reference-integrate phase, VIN is connected to temperature stability (typically 35ppm/°c). This potential can
–
analog common. If VIN is not externally connected to analog be used to generate the TC7126A's reference voltage. An
common, a common-mode voltage exists, but is rejected by external voltage reference will be unnecessary in most
the converter's 86 dB common-mode rejection ratio. In cases because of the 35ppm/°C temperature coefficient.
–
battery operation, analog common and VIN are usually See "TC7126A Internal Voltage Reference" discussion.
connected, removing common-mode voltage concerns. In
–
systems where VIN is connected to power supply ground TEST (Pin 37)
or to a given voltage, analog common should be connected The TEST pin potential is 5V less than V+. TEST may be
–
to VIN . used as the negative power supply connection for external
The analog common pin serves to set the analog section CMOS logic. The TEST pin is tied to the internally-generated
reference, or common point. The TC7126A is specifically negative logic supply through a 500Ω resistor. The TEST pin
designed to operate from a battery or in any measurement load should not be more than 1 mA. See "Digital Section" for
system where input signals are not referenced (float) with additional information on using TEST as a negative digital
logic supply.
If TEST is pulled HIGH (to V+), all segments plus the
INPUT CI
minus sign will be activated. DO NOT OPERATE IN THIS
BUFFER
RI MODE FOR MORE THAN SEVERAL MINUTES. With
+ +
– TEST= V+, the LCD segments are impressed with a DC
VIN
– VI voltage which will destroy the LCD.
+
INTEGRATOR
– TC7126A Internal Voltage Reference
TI The TC7126A's analog common voltage temperature
VCM
VI =
RI CI [V CM – VIN [ stability has been significantly improved (Figure 7). The "A"
Where:
4000 version of the industry-standard TC7126 device allows
T I = Integration time =
f OSC users to upgrade old systems and design new systems
C I = Integration capacitor without external voltage references. External R and C val-
R I = Integration resistor ues do not need to be changed. Figure 10 shows analog
common supplying the necessary voltage reference for the
Figure 6. Common-Mode Voltage Reduces Available Integrator TC7126A.
Swing (VCOM ≠ VIN)

10
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A

200 9V
+
TEMPERATURE COEFFICIENT (ppm/°C)

180
NO
160 MAXIMUM 26 1
SPECIFIED
V– V+ 240 kΩ
ANALOG COMMON

140 TYPICAL

120
TC7126A
NO
100
GUARANTEED MAXIMUM + 36
VREF 10 kΩ
MAXIMUM SPECIFIED
80 VREF
TYPICAL
60 – 35
VREF
TYPICAL
40 ANALOG 32
COMMON
20
TC7126A ICL7126 ICL7136 SET VREF = 1/2 VFULL SCALE
0

Figure 7. Analog Common Temperature Coefficient Figure 8. TC7126A Internal Voltage Reference Connection

Flat Package
APPLICATIONS INFORMATION The TC7126A is available in an epoxy 64-pin formed-
Liquid Crystal Display Sources lead flat package. A test socket for the TC7126ACBQ device
is available:
Several manufacturers supply standard LCDs to inter-
face with the TC7126A 3-1/2 digit analog-to-digital con- Part No. IC 51-42
verter. Manufacturer: Yamaichi
Representative Distribution: Nepenthe Distribution
Manufacturer Address/Phone Part Numbers* 2471 East Bayshore
Crystaloid 5282 Hudson Dr., C5335, H5535, Suite 520
Electronics Hudson, OH 44236 T5135, SX440 Palo Alto, CA 94043
216-655-2429 (415) 856-9332
AND 720 Palomar Avenue FE 0801,
Sunnyvale, CA 94086 FE 0203 Ratiometric Resistance Measurements
408-523-8200
The TC7126A's true differential input and differential
VGI, Inc. 1800 Vernon St., Ste. 2 I1048, I1126 reference make ratiometric readings possible. In ratiometric
Roseville, CA 95678 operation, an unknown resistance is measured with respect
916-783-7878
to a known standard resistance. No accurately-defined
Hamlin, Inc. 612 E. Lake St., 3902, 3933, 3903 reference voltage is needed.
Lake Mills, WI 53551
The unknown resistance is put in series with a known
414-648-2361
standard and a current passed through the pair. The voltage
*NOTE: Contact LCD manufacturer for full product listing/specifications.
developed across the unknown is applied to the input and
the voltage across the known resistor applied to the refer-
Decimal Point and Annunciator Drive ence input. If the unknown equals the standard, the display
will read 1000. The displayed reading can be determined
The TEST pin is connected to the internally-generated
from the following expression:
digital logic supply ground through a 500Ω resistor. The
TEST pin may be used as the negative supply for external RUNKNOWN
Displayed reading = 3 1000.
CMOS gate segment drivers. LCD annunciators for decimal RSTANDARD
points, low battery indication, or function indication may be
The display will overrange for RUNKNOWN ≥
added without adding an additional supply. No more than 1
2 3RSTANDARD.
mA should be supplied by the TEST pin: its potential is
approximately 5V below V+.
11
 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A

Simple Inverter for Fixed Decimal Point

or Display Annunciator +
VREF V+
V+ R STANDARD V–
REF
V+
+ LCD
4049 V IN
TC7126A R UNKNOWN TC7126A
TO LCD
BP 21 DECIMAL
POINT –
V IN
37 GND
TEST ANALOG
TO COMMON
BACKPLANE

Multiple Decimal Point or Figure 10. Low Parts Count Ratiometric Resistance Measurement
Annunciator Driver
V+
V+ BP

DECIMAL TO LCD
POINT DECIMAL
TC7126A SELECT POINTS

TEST 4030
GND

Figure 9. Decimal Point and Annunciator Drives

9V

+
+

1N4148 26
200 mV 1 µF 27
VIN 1 MΩ 1 14
1
V+ V–

2 13 29
9 MΩ C1 0.02 10 MΩ 240 kΩ
µF 3 12
2V TC7126A
4 AD636 11 36 +
10 kΩ V REF
35 – 28
900 kΩ C2 47 kΩ 6.8 µF 5 10 V REF
1W + 32 ANALOG
20V 10% 6 9
1 MΩ 10% COMMON 40
31 +
7 8 V IN
0.01
90 kΩ 2.2 µF 30
20 kΩ µF + 38
200V 10% V OUT

26 39
V–
10 kΩ
BP
SEGMENT
C1 = 3 pF TO 10 pF, VARIABLE DRIVE
COM C2 = 132 pF, VARIABLE

LCD
Figure 11. 3-1/2 Digit True RMS AC DMM
12
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A

+ 9V + 9V

5.6 kΩ 160 kΩ
160 kΩ 300 kΩ 300 kΩ
V+ V– V+ V–
– R1 –
VIN 1N4148 VIN
20 kΩ
R1 + +
1N4148 VIN VIN
SENSOR 50 kΩ
0.7%/°C R3 R2 + TC7126A
R2 + TC7126A PTC VREF
VREF 20 kΩ
50 kΩ
– –
VREF VREF

COMMON COMMON

Figure 12. Temperature Sensor Figure 13. Positive Temperature Coefficient Resistor
Temperature Sensor

9V

2 CONSTANT 5V
V+ V+
+
VREF
51 kΩ 51 kΩ
6
VOUT 50 kΩ
R4 R5 R2 –
VREF
5 2 – 8
ADJ NC
1/2 1 +
LM358 VIN
REF02 3 3
TEMP + TC7126A
TEMPERATURE 4 –
DEPENDENT OUTPUT VIN
VOUT =
50 kΩ
1.86V @ R1 COMMON
+25°C
GND V–
4

Figure 14. Integrated Circuit Temperature Sensor

13
 3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
PACKAGE DIMENSIONS

40-Pin PDIP

PIN 1

.555 (14.10)
.530 (13.46)

2.065 (52.45) .610 (15.49)

2.035 (51.49) .590 (14.99)

.200 (5.08)
.140 (3.56)
.040 (1.02)
.020 (0.51) .015 (0.38)
.150 (3.81) 3° MIN.
.115 (2.92) .008 (0.20)

.700 (17.78)
.610 (15.50)
.110 (2.79) .070 (1.78) .022 (0.56)
.090 (2.29) .045 (1.14) .015 (0.38)

44-Pin PLCC

PIN 1

.050 (1.27) TYP. .021 (0.53)

.013 (0.33)
.695 (17.65)
.685 (17.40)
.630 (16.00)
.656 (16.66) .590 (15.00)
.650 (16.51)
.032 (0.81)
.026 (0.66)

.020 (0.51) MIN.

.656 (16.66)
.650 (16.51) .120 (3.05)
.695 (17.65) .090 (2.29)
.650 (17.40)

.180 (4.57)
.165 (4.19)

Dimensions: inches (mm)

14
3-1/2 DIGIT
ANALOG-TO-DIGITAL CONVERTERS
TC7126
TC7126A
PACKAGE DIMENSIONS (Cont.)

44-Pin PQFP

7° MAX.

.009 (0.23)
PIN 1 .005 (0.13) .041 (1.03)
.026 (0.65)
.018 (0.45)
.012 (0.30) .398 (10.10)
.390 (9.90)
.557 (14.15)
.031 (.080) TYP. .537 (13.65)

.010 (0.25) TYP.

.398 (10.10)
.390 (9.90) .083 (2.10)
.075 (1.90)
.557 (14.15)
.537 (13.65) .096 (2.45) MAX.

Dimensions: inches (mm)

Sales Offices
TelCom Semiconductor TelCom Semiconductor TelCom Semiconductor H.K. Ltd.
1300 Terra Bella Avenue Austin Product Center 10 Sam Chuk Street, Ground Floor
P.O. Box 7267 9101 Burnet Rd. Suite 214 San Po Kong, Kowloon
Mountain View, CA 94039-7267 Austin, TX 78758 Hong Kong
TEL: 650-968-9241 TEL: 512-873-7100 TEL: 852-2324-0122
FAX: 650-967-1590 FAX: 512-873-8236 FAX: 852-2354-9957
E-Mail: liter@c2smtp.telcom-semi.com
Printed in the U.S.A.

15