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1-Wire 4Kb EEPROM DS24B33

General Description Features

The DS24B33 is a 4096-bit, 1-Wire® EEPROM organized ● 4096 Bits of Nonvolatile EEPROM Partitioned Into
as 16 memory pages of 256 bits each. Data is written Sixteen 256-Bit Pages
to a 32-byte scratchpad, verified, and then copied to the ● Read and Write Access is Highly Backward-
EEPROM memory. The DS24B33 communicates over a Compatible to the DS2433
single-conductor 1-Wire bus. The communication follows ● 256-Bit Scratchpad with Strict Read/Write
the standard 1-Wire protocol. Each device has its own unal- ● Protocols Ensures Integrity of Data Transfer
terable and unique 64-bit registration number that is factory Unique, Factory-Programmed, 64-Bit Registration
programmed into the chip. The registration number is used ● Number Ensures Error-Free Device Selection and
to address the device in a multidrop 1-Wire net environ- Absolute Part Identity
ment. The DS24B33 is software compatible to the DS2433. ● Switchpoint Hysteresis to Optimize Performance
in the Presence of Noise
Applications ● Communicates to Host at 15.4kbps or 125kbps
● Storage of Calibration Constants Using 1-Wire Protocol
● Board Identification ● Low-Cost Through-Hole and SMD Packages
● Storage of Product Revision Status ● Operating Range: +2.8V to +5.25V, -40°C to +85°C
● Enhanced ESD Protection

Typical Operating Circuit Ordering Information

PART TEMP RANGE PIN-PACKAGE
VCC DS24B33+ -40°C to +85°C 2 TO-92
DS24B33+T&R -40°C to +85°C 2 TO-92
RPUP
DS24B33G+T&R -40°C to +85°C 2 SFN (2.5k pcs)
IO
DS24B33Q+T&R -40°C to +85°C 6 TDFN-EP* (2.5k pcs)
DS24B33S+ -40°C to +85°C 8 SO (208 mils)
μC DS24B33 DS24B33AS+ -40°C to +85°C 8 SO (208 mils)
DS24B33S+T&R -40°C to +85°C 8 SO (208 mils, 2.5k pcs)
DS24B33AS+T -40°C to +85°C 8 SO (208 mils, 2.5k pcs)
GND Note: The leads of TO-92 packages on tape and reel are
formed to approximately 100-mil (2.54mm) spacing. For details,
refer to the package outline drawing.
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = T = Tape and reel.
*EP = Exposed pad.

1-Wire is a registered trademark of Maxim Integrated Products,

Inc.
19-5759; Rev 6; 9/24

© 2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887 U.S.A. | Tel: 781.329.4700 | © 2024 Analog Devices, Inc. All rights reserved.
DS24B33 1-Wire 4Kb EEPROM

Absolute Maximum Ratings

IO Voltage Range to GND........................................-0.5V to +6V Soldering Temperature (reflow)
IO Sink Current...................................................................20mA TO-92............................................................................+250°C
Operating Temperature Range............................ -40°C to +85°C All other packages, excluding SFN.............................. +260°C
Junction Temperature.......................................................+150°C ESD Rating:
Storage Temperature Range............................. -55°C to +125°C DS24B33:...... ±8kV Contact Discharge, ±15kV Air Discharge,
Lead Temperature (soldering, 10s).................................. +300°C Typical (IEC 1000-4-2 Level 4)
DS24B33A:........................... ±8kV Human Body Model (HBM)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.

Electrical Characteristics
(TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

IO PIN: GENERAL DATA
1-Wire Pullup Voltage VPUP (Notes 2, 3) 2.8 5.25 V
1-Wire Pullup Resistance RPUP (Notes 2, 4) 0.3 2.2 kΩ
DS24B33 2000 pF
Input Capacitance CIO (Notes 5, 6)
DS24B33A 220 nF
DS24B33 0.05 5
Input Load Current IL IO at VPUPMAX µA
DS24B33A 0.05 30
VPUP -
DS24B33 0.5
1.8
High-to-Low Switching Threshold VTL (Notes 6, 7, 8) V
0.55 x
DS24B33A
VPUP
Input Low Voltage VIL (Notes 2, 9) 0.5 V
VPUP -
DS24B33 1.0
1.0
Low-to-High Switching Threshold VTH (Notes 6, 7, 10) V
0.65 x
DS24B33A
VPUP
DS24B33 0.2 1.7 V
Switching Hysteresis VHY (Notes 6, 7, 11)
DS24B33A 0.3 V
Output Low Voltage VOL At 4mA (Note 12) 0.4 V
Standard speed 5
Overdrive speed 2
DS24B33 VPUP ≥ +4.5V 1 µs
Directly prior to reset pulse ≤ 640µs 5
Recovery Time
tREC Directly prior to reset pulse > 640µs 10
(Notes 2, 13)
Standard speed 5
Overdrive speed 2
DS24B33A µs
Directly prior to reset pulse ≤ 640µs 5
Directly prior to reset pulse > 640µs 10

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DS24B33 1-Wire 4Kb EEPROM

Electrical Characteristics (continued)

(TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Standard speed 65
Standard speed, VPUP ≥ +4.5V 61
DS24B33 µs
Time-Slot Duration Overdrive speed 8
tSLOT
(Notes 2, 14) Overdrive speed, VPUP ≥ +4.5V 7
Standard speed 65
DS24B33A µs
Overdrive speed 8
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE
Standard speed, tREC before
480 960
reset = 10µs
Reset Low Time
tRSTL Standard speed, tREC before µs
(Note 2) 480 640
reset = 5µs
Overdrive speed 48 80
Standard speed 15 60
Presence-Detect High Time tPDH µs
Overdrive speed 2 6
Standard speed 60 240
Presence-Detect Low Time tPDL µs
Overdrive speed 8 24
Presence-Detect Sample Time Standard speed 60 75
tMSP µs
(Notes 2, 15) Overdrive speed 6 10
IO PIN: 1-Wire WRITE
Write-Zero Low Time Standard speed 60 120
tW0L µs
(Notes 2, 16) Overdrive speed 6 16
Standard speed 5 15
DS24B33 µs
Write-One Low Time Overdrive speed 1 2
tW1L
(Notes 2, 16) Standard speed 1 15
DS24B33A µs
Overdrive speed 0.25 2
IO PIN: 1-Wire READ
Standard speed 5 15 - d
DS24B33
Read Low Time Overdrive speed 1 2-d
tRL µs
(Notes 2, 17) Standard speed 5 15 - d
DS24B33A
Overdrive speed 0.25 2-d
Read Sample Time Standard speed tRL + d 15
tMSR µs
(Notes 2, 17) Overdrive speed tRL + d 2
EEPROM
Programming Current IPROG (Note 18) 2 mA
DS24B33 5 ms
Programming Time tPROG (Note 19)
DS24B33A 6 ms

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DS24B33 1-Wire 4Kb EEPROM

Electrical Characteristics (continued)

(TA = -40°C to +85°C.) (Note 1)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

At +25°C 200k
Write/Erase Cycles (Endurance) DS24B33 —
NCY At +85°C (worst case) 50k
(Notes 21, 22)
DS24B33A 100k —
DS24B33 At +85°C (worst case) 40 years
Data Retention (Notes 22, 23, 24) tDR
DS24B33A At +85°C (worst case) 25 years
POWER-UP
Power-up Time tOSCWUP DS24B33A (Notes 2, 25) 2 ms

Note 1: Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: System requirement.
Note 3: When operating near the minimum operating voltage (2.8V), a falling edge slew rate of 15V/μs or faster is recommended.
Note 4: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times,
and current requirements during EEPROM programming. The specified value here applies to systems with only one device
and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the
DS2482-x00 or DS2480B may be required.
Note 5: Capacitance on the data pin could be CIO when VPUP is first applied. Once the parasite capacitance is charged, it does not
affect normal communication.
Note 6: Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note 7: VTL, VTH, and VHY are a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and
capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of
VTL, VTH, and VHY.
Note 8: Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 9: The voltage on IO must be less than or equal to VILMAX at all times while the master is driving IO to a logic 0 level.
Note 10: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 11: After VTH is crossed during a rising edge on IO, the voltage on IO must drop by at least VHY to be detected as logic 0.
Note 12: The I-V characteristic is linear for voltages less than +1V.
Note 13: Applies to a single DS24B33 attached to a 1-Wire line.
Note 14: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).
Note 15: Interval after tRSTL during which a bus master can read a logic 0 on IO if there is a DS24B33 present. The power-up
presence detect pulse could be outside this interval but will be complete within 2ms after power-up.
Note 16: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
Note 17: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high
threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
Note 18: Current drawn from IO during the EEPROM programming interval. The pullup circuit on IO should be such that during the
programming interval, the voltage at IO is greater than or equal to VPUPMIN. If VPUP in the system is close to VPUPMIN,
then a low-impedance bypass of RPUP, which can be activated during programming, may need to be added.
Note 19: The tPROG interval begins after the trailing rising edge on IO for the last time slot of the E/S byte for a valid copy scratch-
pad sequence. The interval ends once the device’s self-timed EEPROM programming cycle is complete and the current
drawn by the device has returned from IPROG to IL.
Note 20: Write-cycle endurance is degraded as TA increases.
Note 21: Not 100% production tested; guaranteed by reliability monitor sampling.
Note 22: Data retention is degraded as TA increases.
Note 23: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data
sheet limit at operating temperature range is established by reliability testing.
Note 24: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-time storage at elevated tem-
peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.
Note 25: 1-Wire communication should not take place for at least tOSCWUP after VPUP reaches VPUPMIN.

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DS24B33 1-Wire 4Kb EEPROM

Pin Configurations

SIDE VIEW FRONT VIEW

TOP VIEW
GND 1 1
+
IO 2 2
N.C. 1 8 N.C.
N.C. 3 3

N.C. 2 7 N.C. FRONT VIEW (T&R VERSION)

DS24B33 TO-92
1
IO 3 6 N.C.

2
GND 4 5 N.C.

SO
(208 mils) 3

TOP VIEW BOTTOM VIEW

1 2
DS24B33
+
N.C. 1 6 N.C.

DS24B33
24B33
ymrrF

IO 2 5 N.C. IO GND

GND 3 4 N.C.
*EP
SFN
(6mm x 6mm x 0.9mm)

TDFN
(3mm x 3mm) NOTE: THE SFN PACKAGE IS QUALIFIED FOR ELECTRO-MECHANICAL CONTACT
*EXPOSED PAD
APPLICATIONS ONLY, NOT FOR SOLDERING. FOR MORE INFORMATION, REFER TO
THE ATTACHMENT METHODS FOR ELECTRO-MECHANICAL 1-Wire CONTACT PACKAGE
APPLICATION NOTE.

Pin Description
PIN
SFN TDFN-EP TO-92 SO NAME FUNCTION
2 3 1 4 GND Ground Reference
1 2 2 3 IO 1-Wire Bus Interface. Open-drain pin that requires external pullup resistor.
— 1, 4, 5, 6 3 1, 2, 5–8 N.C. Not Connected
Exposed Pad (TDFN only). Solder evenly to the board’s ground plane
— — — — EP for proper operation. Refer to the Exposed Pads: A Brief Introduction
application note for additional information.

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DS24B33 1-Wire 4Kb EEPROM

Detailed Description Overview

The DS24B33 combines 4Kb of data EEPROM with a fully Figure 1 shows the relationships between the major control
featured 1-Wire interface in a single chip. The memory is and memory sections of the DS24B33. The DS24B33 has
organized as 16 pages of 256 bits each. A volatile 256-bit four main data components: 64-bit registration number,
memory page called the scratchpad acts as a buffer when 32-byte scratchpad, sixteen 32-byte pages of EEPROM,
writing data to the EEPROM to ensure data integrity. Data and a CRC-16 generator. Figure 2 shows the hierarchi-
is first written to the scratchpad, from which it can be read cal structure of the 1-Wire protocol. The bus master must
back for verification before transferring it to the EEPROM. first provide one of the seven ROM (network) function
The operation of the DS24B33 is controlled over the single- commands: Read ROM, Match ROM, Search ROM, Skip
conductor 1-Wire bus. Device communication follows the ROM, Resume, Overdrive-Skip ROM, or Overdrive-Match
standard 1-Wire protocol. The energy required to read and ROM. Upon completion of an overdrive ROM command
write the DS24B33 is derived entirely from the 1-Wire com- byte executed at standard speed, the device enters over-
munication line. Each DS24B33 has its own unalterable and drive mode where all subsequent communication occurs
unique 64-bit registration number. The registration number at a higher speed. Figure 9 describes the protocol required
guarantees unique identification and is used to address for these ROM function commands. After a ROM function
the device in a multidrop 1-Wire net environment. Multiple command is successfully executed, the memory functions
DS24B33 devices can reside on a common 1-Wire bus become accessible and the master can provide any one of
and be operated independently of each other. Applications the four memory function commands. Figure 7 describes
of the DS24B33 include calibration data storage, PCB the protocol for these commands. All data is read and
identification, and storage of product revision status. The written least significant bit (LSB) first.
DS24B33 provides a high degree of backward compatibility
with the DS2433, including having the same family code.

PARASITE POWER

1-Wire NET

1-Wire FUNCTION 64-BIT REGISTRATION

CONTROL NUMBER

MEMORY
FUNCTION
CONTROL UNIT

CRC-16
DS24B33 GENERATOR
32-BYTE
SCRATCHPAD
DATA MEMORY
16 PAGES OF
32 BYTES EACH

Figure 1. Block Diagram

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DS24B33 1-Wire 4Kb EEPROM

Parasite Power gates as shown in Figure 4. The polynomial is X8 + X5 + X4

Figure 1 shows the parasite power supply. This circuitry + 1. Additional information about the 1-Wire CRC is avail-
“steals” power whenever the IO input is high. IO provides able in the Understanding and Using Cyclic Redundancy
sufficient power as long as the specified timing and voltage Checks with Maxim iButton® Products application note.
requirements are met. The shift register bits are initialized to 0. Then, starting
with the LSB of the family code, one bit at a time is shifted
64-Bit Registration Number in. After the 8th bit of the family code has been entered,
Each DS24B33 contains a unique registration number that the serial number is entered. After the last bit of the serial
is 64 bits long. The first 8 bits are a 1-Wire family code. The number has been entered, the shift register contains the
next 48 bits are a unique serial number. The last 8 bits are CRC value. Shifting in the 8 bits of the CRC returns the
a cyclic redundancy check (CRC) of the first 56 bits. See shift register to all 0s.
Figure 3 for details. The 1-Wire CRC is generated using a
polynomial generator consisting of a shift register and XOR

DS24B33
COMMAND LEVEL: AVAILABLE COMMANDS: DATA FIELD AFFECTED:
READ ROM 64-BIT REG. #, RC-FLAG
MATCH ROM 64-BIT REG. #, RC-FLAG
SEARCH ROM 64-BIT REG. #, RC-FLAG
1-Wire ROM
SKIP ROM RC-FLAG
FUNCTION COMMANDS
RESUME RC-FLAG
OVERDRIVE-SKIP ROM RC-FLAG, OD-FLAG
OVERDRIVE-MATCH ROM 64-BIT REG. #, RC-FLAG, OD-FLAG

WRITE SCRATCHPAD 32-BYTE SCRATCHPAD, FLAGS

DS24B33-SPECIFIC READ SCRATCHPAD 32-BYTE SCRATCHPAD
MEMORY FUNCTION COMMANDS COPY SCRATCHPAD DATA MEMORY
READ MEMORY DATA MEMORY

Figure 2. Hierarchical Structure for 1-Wire Protocol

MSB LSB

8-BIT 8-BIT FAMILY CODE

48-BIT SERIAL NUMBER
CRC CODE (23h)

MSB LSB MSB LSB MSB LSB

Figure 3. 64-Bit Registration Number

iButton is a registered trademark of Maxim Integrated Products, Inc.

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DS24B33 1-Wire 4Kb EEPROM

Memory Memory Access

The DS24B33 EEPROM array (Figure 5) consists of 16 Address Registers and Transfer Status
pages of 32 bytes each, starting at address 0000h and
The DS24B33 employs three address registers: TA1, TA2,
ending at address 01FFh. In addition to the EEPROM,
and E/S (Figure 6). Registers TA1 and TA2 must be load-
the device has a 32-byte volatile scratchpad. Writes to
ed with the target address to which the data is written or
the EEPROM array are a two-step process. First, data is
from which data is read. Register E/S is a read-only trans-
written to the scratchpad and then copied into the main
fer status register used to verify data integrity with write
array. The user can verify the data in the scratchpad prior
commands. ES bits E[4:0] are loaded with the incoming
to copying.

POLYNOMIAL = X8 + X5 + X4 + 1

1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH

STAGE STAGE STAGE STAGE STAGE STAGE STAGE STAGE

X0 X1 X2 X3 X4 X5 X6 X7 X8

INPUT DATA

Figure 4. 1-Wire CRC Generator

32-BYTE INTERMEDIATE STORAGE SCRATCHPAD

ADDRESS

0000h to 001Fh 32-BYTE FINAL STORAGE EEPROM PAGE 0

0020h to 003Fh 32-BYTE FINAL STORAGE EEPROM PAGE 1

0040h to 01DFh FINAL STORAGE EEPROM PAGES 2 to 14

01E0h to 01FFh 32-BYTE FINAL STORAGE EPPROM PAGE 15

Figure 5. Memory Map

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DS24B33 1-Wire 4Kb EEPROM

T[4:0] on a Write Scratchpad command and increment the target address TA1 and TA2 and sends the contents
on each subsequent data byte. This is, in effect, a byte- of the E/S register. If the PF flag is set, data did not arrive
ending offset counter within the 32-byte scratchpad. Bit correctly in the scratchpad or there was a loss of power
5 of the E/S register, called the partial byte flag (PF), is since data was last written to the scratchpad. The master
set if the number of data bits sent by the master is not an does not need to continue reading; it can start a new trial
integer multiple of 8 or if the data in the scratchpad is not to write data to the scratchpad. Similarly, a set AA flag
valid due to a loss of power. A valid write to the scratchpad together with a cleared PF flag indicates that the device
clears the PF bit. Bit 6 has no function; it always reads 0. did not recognize the write command. If everything went
The highest valued bit of the E/S register, called authori- correctly, both flags are cleared and the ending offset indi-
zation accepted (AA), is valid only if the PF flag reads 0. cates the address of the last byte written to the scratch-
If PF is 0 and AA is 1, the data stored in the scratchpad pad. Now the master can continue reading and verifying
has already been copied to the target memory address. every data byte. After the master has verified the data, it
Writing data to the scratchpad clears this flag. can send the Copy Scratchpad command, for example.
This command must be followed exactly by the data of the
Writing with Verification three address registers TA1, TA2, and E/S. The master
To write data to the DS24B33, the scratchpad must be should obtain the contents of these registers by reading
used as intermediate storage. First, the master issues the scratchpad. As soon as the DS24B33 has received
the Write Scratchpad command to specify the desired these bytes correctly, it starts copying the scratchpad data
target address, followed by the data to be written to to the requested location.
the scratchpad. Under certain conditions (see the Write
Scratchpad [0Fh] section) the master receives an inverted Memory Function Commands
CRC-16 of the command, address, and data at the end of The Memory Function Flowchart (Figure 7) describes
the Write Scratchpad command sequence. Knowing this the protocols necessary for accessing the memory of
CRC value, the master can compare it to the value it has the DS24B33. The target address registers TA1 and TA2
calculated itself to decide if the communication was suc- are used for both read and write. The communication
cessful and proceed to the Copy Scratchpad command. If between the master and the DS24B33 takes place either
the master could not receive the CRC-16, it should send at standard speed (default, OD = 0) or at overdrive speed
the Read Scratchpad command to verify data integrity. As (OD = 1). If not explicitly set into the overdrive mode, the
a preamble to the scratchpad data, the DS24B33 repeats DS24B33 assumes standard speed.

BIT NUMBER 7 6 5 4 3 2 1 0

TARGET ADDRESS (TA1) T7 T6 T5 T4 T3 T2 T1 T0

TARGET ADDRESS (TA2) T15 T14 T13 T12 T11 T10 T9 T8

ENDING ADDRESS WITH

DATA STATUS (E/S) AA 0 PF E4 E3 E2 E1 E0
(READ ONLY)

Figure 6. Address Registers

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DS24B33 1-Wire 4Kb EEPROM

Write Scratchpad [0Fh] Copy Scratchpad [55h]

The Write Scratchpad command applies to the data mem- The Copy Scratchpad command is used to copy data
ory. After issuing the Write Scratchpad command, the mas- from the scratchpad to the data memory. After issuing
ter must first provide the 2-byte target address, followed by the Copy Scratchpad command, the master must provide
the data to be written to the scratchpad. The data is written a 3-byte authorization pattern, which should have been
to the scratchpad starting at the byte offset of T[4:0]. The obtained by an immediately preceding Read Scratchpad
ES bits E[4:0] are loaded with the starting byte offset and command. This 3-byte pattern must exactly match the
increment with each subsequent byte. Effectively, E[4:0] is data contained in the three address registers (TA1, TA2,
the byte offset of the last full byte written to the scratchpad. E/S, in that order). If the pattern matches and the target
Only full bytes are accepted. If the last byte is incomplete, address is valid, the AA flag is set and the copy begins.
its content is ignored and PF is set. The data to be copied is determined by the three address
When executing the Write Scratchpad command, the CRC registers. The scratchpad data from the beginning offset
generator inside the DS24B33 (Figure 13) calculates a through the ending offset is copied to memory, starting at
16-bit CRC of the entire data stream, starting at the com- the target address. Anywhere from 1 to 32 bytes can be
mand code and ending at the last data byte as sent by copied with this command. The duration of the device’s
the master. This CRC is generated using the CRC-16 internal data transfer is tPROG, during which the voltage
polynomial (X16 + X15 + X2 + 1) by first clearing the CRC on the 1-Wire bus must not fall below VPUPMIN. A pattern
generator and then shifting in the command code (0Fh) of of alternating 0s and 1s are transmitted after the data has
the Write Scratchpad command, the target addresses TA1 been copied until the master issues a reset pulse.
and TA2 as supplied by the master, and all the data bytes. Note: Because of the memory architecture of the
The master can end the Write Scratchpad command at DS24B33, if a Copy Scratchpad command is interrupted
any time. However, if the end of the scratchpad is reached during the write cycle, two consecutive Copy Scratchpad
(E[4:0] = 11111b), the master can send 16 read time slots commands of the same data to the same location may be
to receive the CRC generated by the DS24B33. necessary to recover. To verify the success of the Copy
The DS24B33’s memory address range is 0000h to Scratchpad command, always look for the alternating
01FFh. If the bus master sends a target address higher 0-to-1 pattern at the end of the Copy Scratchpad com-
than this, the DS24B33’s internal circuitry sets the 7 most mand flow and also read back the EEPROM page that
significant address bits to zero as they are shifted into the was to be updated. If the alternating pattern appeared
internal address register. The Read Scratchpad command and the EEPROM page data shows the intended new
reveals the modified target address. The master identi- data, the write access was successful. No further action
fies such address modifications by comparing the target is required. In all other cases (alternating 0-to-1 pattern
address read back to the target address transmitted. If the is not seen or nonmatching EEPROM page data), repeat
master does not read the scratchpad, a subsequent Copy the Write Scratchpad, Copy Scratchpad sequence until
Scratchpad command does not work because the most successful.
significant bits of the target address the master sends do
not match the value that the DS24B33 expects.
Read Scratchpad [AAh]
The Read Scratchpad command allows for verifying the
target address and the integrity of the scratchpad data.
After issuing the command code, the master begins read-
ing. The first 2 bytes are the target address. The next byte
is the ending offset/data status byte (E/S) followed by the
scratchpad data beginning at the byte offset (T[4:0]). The
master should read through the end of the scratchpad.
If the master continues reading beyond the end of the
scratchpad, all data are logic 1s.

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DS24B33 1-Wire 4Kb EEPROM

BUS MASTER Tx MEMORY FROM ROM FUNCTIONS

FUNCTION COMMAND FLOWCHART (FIGURE 9)

0Fh N AAh N TO FIGURE 7b

WRITE SCRATCHPAD? READ SCRATCHPAD?

Y Y

DS24B33 CLEARS PF, AA BUS MASTER Rx

TA1 (T[7:0]), TA2 (T[15:8]),
AND E/S BYTE
BUS MASTER Tx EEPROM
ARRAY TARGET ADDRESS
TA1 (T[7:0]), TA2 (T[15:8]) DS24B33 SETS SCRATCHPAD
OFFSET = (T[4:0])

DS24B33 SETS SCRATCHPAD

OFFSET = (T[4:0])
BUS MASTER Rx DATA BYTE
TO SCRATCHPAD OFFSET

MASTER Tx DATA BYTE

TO SCRATCHPAD OFFSET DS24B33
INCREMENTS
SCRATCHPAD Y
MASTER Tx RESET?
OFFSET
DS24B33 DS24B33 SETS (E[4:0]) =
INCREMENTS SCRATCHPAD OFFSET N
SCRATCHPAD
OFFSET
N
SCRATCHPAD OFFSET
Y
MASTER Tx RESET? = 11111b?

Y
N
N
PARTIAL BYTE?

N
SCRATCHPAD OFFSET Y
= 11111b?

Y PF = 1

DS24B33 Tx CRC-16 OF
COMMAND, ADDRESS,
AND DATA BYTES AS THEY
WERE SENT BY THE BUS
MASTER

BUS MASTER N BUS MASTER N

MASTER Tx RESET? MASTER Tx RESET?
Rx "1"s Rx "1"s

Y Y
FROM FIGURE 7b

TO ROM FUNCTIONS
FLOWCHART (FIGURE 9)

Figure 7a. Memory Function Flowchart

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DS24B33 1-Wire 4Kb EEPROM

FROM FIGURE 7a 55h N F0h N

COPY SCRATCHPAD? READ MEMORY?

Y Y

BUS MASTER Rx BUS MASTER Tx

TA1 (T[7:0]), TA2 (T[15:8]), TA1 (T[7:0]), TA2 (T[15:8])
AND E/S BYTE

BUS MASTER
AUTHORIZATION Y Rx "1"s
CODE MATCH?

N
N
MASTER Tx RESET?

AA = 1 DS24B33 SETS MEMORY

ADDRESS = (T[15:0])

DS24B33 COPIES *
SCRATCHPAD DATA BUS MASTER Rx
TO ADDRESS DATA BYTE FROM
MEMORY ADDRESS

DS24B33
DS24B33 Tx "0" INCREMENTS
ADDRESS
Y
COUNTER MASTER Tx RESET?

Y
MASTER Tx RESET? N

N Y
BUS MASTER ADDRESS < 1FFh?
Rx "1"s DS24B33 Tx "1"
N

N N BUS MASTER N
MASTER Tx RESET? MASTER Tx RESET? MASTER Tx RESET?
Rx "1"s

Y Y Y
TO FIGURE 7a

*1-Wire IDLE HIGH FOR tPROG FOR POWER.

Figure 7b. Memory Function Flowchart (continued)

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DS24B33 1-Wire 4Kb EEPROM

Read Memory [F0h] 1-Wire Bus System

The Read Memory command is the general function to The 1-Wire bus is a system that has a single bus master
read from the DS24B33. After issuing the command, and one or more slaves. In all instances the DS24B33 is
the master must provide a 2-byte target address, which a slave device. The bus master is typically a microcon-
should be in the range of 0000h to 01FFh. If the target troller. The discussion of this bus system is broken down
address is higher than 01FFh, the DS24B33 changes into three topics: hardware configuration, transaction
the upper 7 address bits to 0. After the address is trans- sequence, and 1-Wire signaling (signal types and timing).
mitted, the master reads data starting at the (modified) The 1-Wire protocol defines bus transactions in terms of
target address and can continue until address 01FFh. If the bus state during specific time slots, which are initiated
the master continues reading, the result is FFh. The Read on the falling edge of sync pulses from the bus master.
Memory command can be ended at any point by issuing
a reset pulse. Note that the (modified) target address Hardware Configuration
provided with the Read Memory command overwrites the The 1-Wire bus has only a single line by definition; it is
target address that was specified with a previously issued important that each device on the bus be able to drive
Write Scratchpad command. The Read Memory com- it at the appropriate time. To facilitate this, each device
mand overwrites the scratchpad with data from the target attached to the 1-Wire bus must have open-drain or three-
memory page. When reading the last byte of a memory state outputs. The 1-Wire port of the DS24B33 is open
page, the scratchpad is loaded with data from the next drain with an internal circuit equivalent to that shown in
memory page. This could cause unexpected data to be Figure 8.
loaded into the scratchpad.

VPUP

BUS MASTER DS24B33 1-Wire PORT

RPUP
DATA
Rx Rx

Tx IL Tx
Rx = RECEIVE
Tx = TRANSMIT
OPEN-DRAIN
100Ω MOSFET
PORT PIN

Figure 8. Hardware Configuration

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DS24B33 1-Wire 4Kb EEPROM

A multidrop bus consists of a 1-Wire bus with multiple Read ROM [33h]
slaves attached. The DS24B33 supports both a standard This command allows the bus master to read the
and overdrive communication speed of 15.4kbps (maxi- DS24B33’s 8-bit family code, unique 48-bit serial number,
mum) and 125kbps (maximum), respectively, over the full and 8-bit CRC. This command can only be used if there
pullup voltage range. For pullup voltages of +4.75V and is a single slave on the bus. If more than one slave is
higher, the DS24B33 also supports the legacy communica- present on the bus, a data collision occurs when all slaves
tion speed of 16.3kbps and overdrive speed of 142kbps. try to transmit at the same time (open drain produces a
The slightly reduced rates for the DS24B33 and DS24B33A wired-AND result). The resultant family code and 48-bit
over the full pullup voltage range are a result of additional serial number results in a mismatch of the CRC.
recovery times, which in turn were driven by a 1-Wire
physical interface enhancement to improve noise immunity. Match ROM [55h]
The value of the pullup resistor primarily depends on the The Match ROM command, followed by a 64-bit ROM
network size and load conditions. The DS24B33 requires a sequence, allows the bus master to address a specific
pullup resistor of 2.2kΩ (maximum) at any speed. The idle DS24B33 on a multidrop bus. Only the DS24B33 that
state for the 1-Wire bus is high. If for any reason a transac- exactly matches the 64-bit ROM sequence responds
tion must be suspended, the bus must be left in the idle to the memory function command that follows. All other
state if the transaction is to resume. If this does not occur slaves wait for a reset pulse. This command can be used
and the bus is left low for more than 16μs (overdrive speed) with a single device or multiple devices on the bus.
or more than 120μs (standard speed), one or more devices
on the bus may be reset. Search ROM [F0h]
When a system is initially brought up, the bus master
Transaction Sequence might not know the number of devices on the 1-Wire bus
The protocol for accessing the DS24B33 through the or their registration numbers. By taking advantage of the
1-Wire port is as follows: bus’s wired-AND property, the master can use a process
of elimination to identify the registration numbers of all
● Initialization
slave devices. For each bit of the registration number,
● ROM Function Commands starting with the LSB, the bus master issues a triplet of
● Memory Function Commands time slots. On the first slot, each slave device participating
in the search outputs the true value of its registration num-
● Transaction/Data
ber bit. On the second slot, each slave device participat-
Initialization ing in the search outputs the complemented value of its
registration number bit. On the third slot, the master writes
All transactions on the 1-Wire bus begin with an initializa-
the true value of the bit to be selected. All slave devices
tion sequence. The initialization sequence consists of a
that do not match the bit written by the master stop partici-
reset pulse transmitted by the bus master followed by
pating in the search. If both of the read bits are zero, the
presence pulse(s) transmitted by the slave(s). The pres-
master knows that slave devices exist with both states of
ence pulse lets the bus master know that the DS24B33 is
the bit. By choosing which state to write, the bus master
on the bus and is ready to operate. For more details, see
branches in the ROM code tree. After one complete pass,
the 1-Wire Signaling section.
the bus master knows the registration number of a single
device. Additional passes identify the registration num-
1-Wire ROM Function Commands bers of the remaining devices. Refer to the 1-Wire Search
Once the bus master has detected a presence, it can Algorithm application note for a detailed discussion and
issue one of the seven ROM function commands that the an example.
DS24B33 supports. All ROM function commands are 8
bits long. See Figure 9 for a list of these commands.

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DS24B33 1-Wire 4Kb EEPROM

Skip ROM [CCh] When issued on a multidrop bus, this command sets all
This command can save time in a single-drop bus sys- overdrive-supporting devices into overdrive mode. To
tem by allowing the bus master to access the memory subsequently address a specific overdrive-supporting
functions without providing the 64-bit ROM code. If more device, a reset pulse at overdrive speed must be issued
than one slave is present on the bus and, for example, followed by a Match ROM or Search ROM command
a read command is issued following the Skip ROM com- sequence. This speeds up the time for the search pro-
mand, data collision occurs on the bus as multiple slaves cess. If more than one slave supporting overdrive is pres-
transmit simultaneously (open-drain pulldowns produce a ent on the bus and the Overdrive-Skip ROM command is
wired-AND result). followed by a Read command, data collision occurs on
the bus as multiple slaves transmit simultaneously (open-
Resume [A5h] drain pulldowns produce a wired-AND result).
To maximize the data throughput in a multidrop environ-
ment, the Resume command is available. This command
Overdrive-Match ROM [69h]
checks the status of the RC bit and, if it is set, directly The Overdrive-Match ROM command followed by a 64-bit
transfers control to the memory functions, similar to a ROM sequence transmitted at overdrive speed allows the
Skip ROM command. The only way to set the RC bit is bus master to address a specific DS24B33 on a multi-
by successfully executing the Match ROM, Search ROM, drop bus and to simultaneously set it in overdrive mode.
or Overdrive-Match ROM command. Once the RC bit is Only the DS24B33 that exactly matches the 64-bit ROM
set, the device can repeatedly be accessed through the sequence responds to the subsequent memory function
Resume command. Accessing another device on the bus command. Slaves already in overdrive mode from a previ-
clears the RC bit, preventing two or more devices from ous Overdrive-Skip ROM or successful Overdrive-Match
simultaneously responding to the Resume command. ROM command remain in overdrive mode. All overdrive-
capable slaves return to standard speed at the next reset
Overdrive-Skip ROM [3Ch] pulse of minimum 480μs duration. The Overdrive-Match
On a single-drop bus, this command can save time by ROM command can be used with a single device or mul-
allowing the bus master to access the memory functions tiple devices on the bus.
without providing the 64-bit ROM code. Unlike the normal
Skip ROM command, the Overdrive-Skip ROM command
sets the DS24B33 in the overdrive mode (OD = 1). All
communication following this command must occur at
overdrive speed until a reset pulse of minimum 480μs
duration resets all devices on the bus to standard speed
(OD = 0).

www.analog.com Analog Devices │ 15

DS24B33 1-Wire 4Kb EEPROM

BUS MASTER Tx
RESET PULSE
FROM FIGURE 9b
FROM MEMORY FUNCTIONS
FLOWCHART (FIGURE 7)

OD N
RESET PULSE? OD = 0

BUS MASTER Tx ROM DS24B33 Tx

FUNCTION COMMAND PRESENCE PULSE

33h 55h F0h CCh

N N N N TO FIGURE 9b
READ ROM MATCH ROM SEARCH ROM SKIP ROM
COMMAND? COMMAND? COMMAND? COMMAND?

Y Y Y Y

RC = 0 RC = 0 RC = 0 RC = 0

DS24B33 Tx BIT 0
DS24B33Tx
FAMILY CODE MASTER Tx BIT 0 DS24B33 Tx BIT 0
(1 BYTE) MASTER Tx BIT 0

N N
BIT 0 MATCH? BIT 0 MATCH?

Y
Y
DS24B33 Tx BIT 1
DS24B33 Tx
SERIAL NUMBER MASTER Tx BIT 1 DS24B33 Tx BIT 1
(6 BYTES) MASTER Tx BIT 1

N N
BIT 1 MATCH? BIT 1 MATCH?

Y Y

DS24B33 Tx BIT 63
DS24B33 Tx
MASTER Tx BIT 63 DS24B33 Tx BIT 63
CRC BYTE
MASTER Tx BIT 63

N N
BIT 63 MATCH? BIT 63 MATCH?

Y Y

RC = 1 RC = 1
TO FIGURE 9b

FROM FIGURE 9b

TO MEMORY FUNCTIONS
FLOWCHART (FIGURE 7)

Figure 9a. ROM Functions Flowchart

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DS24B33 1-Wire 4Kb EEPROM

TO FIGURE 9a

A5h 3Ch 69h

FROM FIGURE 9a N N N
RESUME OVERDRIVE- OVERDRIVE-
COMMAND? SKIP ROM? MATCH ROM?

Y Y Y

RC = 0; OD = 1 RC = 0; OD = 1
N
RC = 1?

MASTER Tx Y MASTER Tx BIT 0

RESET?

(SEE NOTE)
MASTER Tx Y N
BIT 0 MATCH? OD = 0
RESET?

N
Y

MASTER Tx BIT 1

(SEE NOTE)
N
BIT 1 MATCH? OD = 0

MASTER Tx BIT 63

(SEE NOTE)
N
BIT 63 MATCH? OD = 0

RC = 1
FROM FIGURE 9a

TO FIGURE 9a

NOTE: THE OD FLAG REMAINS AT 1 IF THE DEVICE WAS ALREADY AT OVERDRIVE SPEED BEFORE THE OVERDRIVE-MATCH ROM COMMAND WAS ISSUED.

Figure 9b. ROM Functions Flowchart (continued)

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DS24B33 1-Wire 4Kb EEPROM

1-Wire Signaling After the bus master has released the line it goes into
The DS24B33 requires strict protocols to ensure data receive mode. Now the 1-Wire bus is pulled to VPUP
integrity. The protocol consists of four types of signaling through the pullup resistor, or in case of a DS2482-x00 or
on one line: reset sequence with reset pulse and presence DS2480B driver, by active circuitry. When the threshold
pulse, write-zero, write-one, and read-data. Except for the VTH is crossed, the DS24B33 waits for tPDH and then
presence pulse, the bus master initiates all falling edges. transmits a presence pulse by pulling the line low for tPDL.
The DS24B33 can communicate at two different speeds: To detect a presence pulse, the master must test the logi-
standard speed and overdrive speed. If not explicitly set cal state of the 1-Wire line at tMSP.
into the overdrive mode, the DS24B33 communicates at The tRSTH window must be at least the sum of tPDH-
standard speed. While in overdrive mode the fast timing MAX, tPDLMAX, and tRECMIN. Immediately after tRSTH is
applies to all waveforms. expired, the DS24B33 is ready for data communication. In
To get from idle to active, the voltage on the 1-Wire line a mixed population network, tRSTH should be extended to
needs to fall from VPUP below the threshold VTL. To get minimum 480μs at standard speed and 48μs at overdrive
from active to idle, the voltage needs to rise from VILMAX speed to accommodate other 1-Wire devices.
past the threshold VTH. The time it takes for the voltage Read/Write Time Slots
to make this rise is seen in Figure 10 as ε, and its dura-
Data communication with the DS24B33 takes place in
tion depends on the pullup resistor (RPUP) used and the
time slots, which carry a single bit each. Write time slots
capacitance of the 1-Wire network attached. The voltage
transport data from bus master to slave. Read time slots
VILMAX is relevant for the DS24B33 when determining a
transfer data from slave to master. Figure 11 illustrates the
logical level, not triggering any events.
definitions of the write and read time slots. All communica-
Figure 10 shows the initialization sequence required to tion begins with the master pulling the data line low. As the
begin any communication with the DS24B33. A reset pulse voltage on the 1-Wire line falls below the threshold VTL,
followed by a presence pulse indicates that the DS24B33 is the DS24B33 starts its internal timing generator that deter-
ready to receive data, given the correct ROM and memory mines when the data line is sampled during a write time slot
function command. If the bus master uses slew-rate control and how long data is valid during a read time slot.
on the falling edge, it must pull down the line for tRSTL +
tF to compensate for the edge. A tRSTL duration of 480μs Master-to-Slave
or longer exits the overdrive mode, returning the device to For a write-one time slot, the voltage on the data line
standard speed. If the DS24B33 is in overdrive mode and must have crossed the VTH threshold before the write-
tRSTL is no longer than 80μs, the device remains in over- one low time tW1LMAX is expired. For a write-zero time
drive mode. If the device is in overdrive mode and tRSTL is slot, the voltage on the data line must stay below the VTH
between 80μs and 480μs, the device resets, but the com- threshold until the write-zero low time tW0LMIN is expired.
munication speed is undetermined. For the most reliable communication, the voltage on the

MASTER Tx "RESET PULSE" MASTER Rx "PRESENCE PULSE"

ε
tMSP
VPUP
VIHMASTER
VTH

VTL
VILMAX
0V
tPDH
tRSTL tPDL tREC
tF
tRSTH

RESISTOR MASTER DS24B33

Figure 10. Initialization Procedure: Reset and Presence Pulse

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DS24B33 1-Wire 4Kb EEPROM

data line should not exceed VILMAX during the entire crossed, the DS24B33 needs a recovery time tREC before
tW0L or tW1L window. After the VTH threshold has been it is ready for the next time slot.

WRITE-ONE TIME SLOT

tW1L
VPUP
VIHMASTER
VTH

VTL
VILMAX
0V
ε
tF
tSLOT

RESISTOR MASTER

WRITE-ZERO TIME SLOT

tW0L
VPUP
VIHMASTER
VTH

VTL
VILMAX
0V
ε
tF tREC
tSLOT

RESISTOR MASTER

READ-DATA TIME SLOT

tMSR
tRL
VPUP
VIHMASTER
VTH MASTER
SAMPLING
VTL WINDOW
VILMAX
0V
δ
tF tREC
tSLOT

RESISTOR MASTER DS24B33

Figure 11. Read/Write Timing Diagrams

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DS24B33 1-Wire 4Kb EEPROM

Slave-to-Master Noise coupled onto the 1-Wire line from external sources
A read-data time slot begins like a write-one time slot. can also result in signal glitching. A glitch during the rising
The voltage on the data line must remain below VTL until edge of a time slot can cause a slave device to lose syn-
the read low time tRL is expired. During the tRL window, chronization with the master and, consequently, result in
when responding with a 0, the DS24B33 starts pulling a Search ROM command coming to a dead end or cause
the data line low; its internal timing generator determines a device-specific function command to abort. For better
when this pulldown ends and the voltage starts rising performance in network applications, the DS24B33 uses
again. When responding with a 1, the DS24B33 does not an improved 1-Wire front-end, which makes it less sensi-
hold the data line low at all, and the voltage starts rising tive to noise. The 1-Wire front-end of the DS24B33 differs
as soon as tRL is over. from traditional slave devices in one characteristic: There
is a hysteresis at the low-to-high switching threshold VTH.
The sum of tRL + δ (rise time) on one side and the internal
If a negative glitch crosses VTH but does not go below
timing generator of the DS24B33 on the other side define
VTH - VHY, it is not recognized (Figure 12). The hysteresis
the master sampling window (tMSRMIN to tMSRMAX) in
is effective at any 1-Wire speed.
which the master must perform a read from the data line.
For the most reliable communication, tRL should be as CRC Generation
short as permissible, and the master should read close
The DS24B33 uses two different types of CRCs. One
to but no later than tMSRMAX. After reading from the data
CRC is an 8-bit type and is stored in the most significant
line, the master must wait until tSLOT is expired. This
byte of the 64-bit registration number. The bus master
guarantees sufficient recovery time tREC for the DS24B33
can compute a CRC value from the first 56 bits of the
to get ready for the next time slot. Note that tREC speci-
64-bit registration number and compare it to the value
fied herein applies only to a single DS24B33 attached to
stored within the DS24B33 to determine if the registra-
a 1-Wire line. For multidevice configurations, tREC needs
to be extended to accommodate the additional 1-Wire tion number has been received error-free. The equivalent
device input capacitance. Alternatively, an interface that polynomial function of this CRC is X8 + X5 + X4 + 1. This
8-bit CRC is received in the true (noninverted) form. It is
performs active pullup during the 1-Wire recovery time
computed and programmed into the chip at the factory.
such as the DS2482-x00 or DS2480B 1-Wire line drivers
can be used. The other CRC is a 16-bit type, generated according to
the standardized CRC-16 polynomial function X16 + X15
Improved Network Behavior + X2 + 1. This CRC is used for fast verification of a data
(Switchpoint Hysteresis) transfer when writing to the scratchpad. In contrast to the
8-bit CRC, the 16-bit CRC is always communicated in
In a 1-Wire environment, line termination is possible only
the inverted form. A CRC generator inside the DS24B33
during transients controlled by the bus master (1-Wire
(Figure 13) calculates a new 16-bit CRC, as shown in the
driver). 1-Wire networks, therefore, are susceptible to
command flowchart (Figure 7). The bus master compares
noise of various origins. Depending on the physical size
the CRC value read from the device to the one it calcu-
and topology of the network, reflections from end points
lates from the data, and decides whether to continue with
and branch points can add up or cancel each other to
an operation.
some extent. Such reflections are visible as glitches or
ringing on the 1-Wire communication line. With the Write Scratchpad command, the CRC is gener-
ated by first clearing the CRC generator and then shifting
in the command code, the target addresses TA1 and
VPUP TA2, and all the data bytes as they were sent by the bus
master. The DS24B33 transmits this CRC only if the data
VTH bytes written to the scratchpad include scratchpad ending
VHY
offset 11111b. The data can start at any location within the
scratchpad.
0V For more information on generating CRC values refer to
the Understanding and Using Cyclic Redundancy Checks
Figure 12. Hysteresis at the Low-to-High Switching Threshold with Maxim iButton Products application note.

www.analog.com Analog Devices │ 20

DS24B33 1-Wire 4Kb EEPROM

POLYNOMIAL = X16 + X15 + X2 + 1

1ST 2ND 3RD 4TH 5TH 6TH 7TH 8TH

STAGE STAGE STAGE STAGE STAGE STAGE STAGE STAGE

X0 X1 X2 X3 X4 X5 X6 X7

9TH 10TH 11TH 12TH 13TH 14TH 15TH 16TH

STAGE STAGE STAGE STAGE STAGE STAGE STAGE STAGE

X8 X9 X10 X11 X12 X13 X14 X15 X16 CRC OUTPUT

INPUT DATA

Figure 13. CRC-16 Hardware Description and Polynomial

Command-Specific 1-Wire Communication Protocol—Legend

SYMBOL DESCRIPTION
RST 1-Wire reset pulse generated by master
PD 1-Wire presence pulse generated by slave
Select Command and data to satisfy the ROM function protocol
WS Command: “Write Scratchpad”
RS Command: “Read Scratchpad”
CPS Command: “Copy Scratchpad”
RM Command: “Read Memory”
TA Target Address TA1, TA2
TA-E/S Target Address TA1, TA2 with E/S byte
<data to EOS> Transfer of as many bytes as needed to reach the end of the scratchpad for a given target address
<data to EOM> Transfer of as many bytes as are needed to reach the end of the memory
CRC-16 Transfer of an inverted CRC-16
FF loop Indefinite loop where the master reads FF bytes
AA loop Indefinite loop where the master reads AA bytes
Programming Data transfer to EEPROM; no activity on the 1-Wire bus permitted during this time

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DS24B33 1-Wire 4Kb EEPROM

Command-Specific 1-Wire Communication Protocol—Color Codes

Master-to-Slave Slave-to-Master Programming

1-Wire Communication Examples

Write Scratchpad, Reaching the End of the Scratchpad

RST PD Select WS TA <data to EOS> CRC-16 FF loop

Read Scratchpad
RST PD Select RS TA-E/S <data to EOS> FF loop

Copy Scratchpad (Success)

RST PD Select CPS TA-E/S Programming AA loop

Copy Scratchpad (Fail TA-E/S)

RST PD Select CPS TA-E/S FF loop

Read Memory
RST PD Select RM TA <data to EOM> FF loop

www.analog.com Analog Devices │ 22

DS24B33 1-Wire 4Kb EEPROM

SFN Package Orientation on Tape and Reel

USER DIRECTION OF FEED

LEADS FACE UP IN ORIENTATION SHOWN ABOVE.
SFN
(6mm x 6mm x 0.9mm)

Package Information
For the latest package outline information and land patterns (footprints), go to www.analog.com/en/resources/packaging-quality-
symbols-footprints/package-index.html. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.

8 SO W8+2 21-0262 90-0258
3 TO-92 (Bulk) Q3+1 21-0248 —
3 TO-92 (T&R) Q3+4 21-0250 —
2 SFN G266N+1 21-0390 —
6 TDFN-EP T633+2 21-0137 90-0058

www.analog.com Analog Devices │ 23

DS24B33 1-Wire 4Kb EEPROM

Revision History
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 2/11 Initial release —
1 5/11 Implemented text changes to better market the document 1
2 3/12 Revised the Electrical Characteristics table notes 1, 5, and 15. 3
3 5/12 Added the SFN (6mm x 6mm x 0.9mm) and TDFN (3mm x 3mm) packages 1, 2, 4, 5, 22
4 2/23 Add DS24B33A part number and related changes. 1– 4, 13
5 5/23 Updated Ordering Information table 1
6 9/24 Removed DS24B33AQ+T from Ordering Information table 1

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is
assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that
may result from its use.Specifications subject to change without notice. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the
property of their respective owners.

w w w . a n a l o g . c o m Analog Devices │ 24